might as well use a cascade fifo to help timing and give a little more capacity

diff --git a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
index 7511f3fb9650a67a93d417ac0695a88948a6c576..71ad0cf0f7bb7e0e42c2b1f018af48c990ffc49e 100644 (file)
--- a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
+++ b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
@@ -110,7 +110,7 @@ module simple_gemac_wrapper
    wire [35:0]           tx_f36_data_int1;
    wire          tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
    
-   fifo_2clock #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
      (.wclk(sys_clk), .datain(tx_f36_data), 
       .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
       .rclk(tx_clk), .dataout(tx_f36_data_int1),