--- /dev/null
+/*-------------------------------------------------------------------------\r
+ Register Declarations for Analog Devices ADuC841/ADuC842/ADuC843\r
+ (Based on datasheet Rev 0, 11/2003 )\r
+\r
+ Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (March 2007)\r
+\r
+ This library is free software; you can redistribute it and/or\r
+ modify it under the terms of the GNU Lesser General Public\r
+ License as published by the Free Software Foundation; either\r
+ version 2.1 of the License, or (at your option); any later version\r
+\r
+ This library is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+ Lesser General Public License for more details\r
+\r
+ You should have received a copy of the GNU Lesser General Public\r
+ License along with this library; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ In other words, you are welcome to use, share and improve this program\r
+ You are forbidden to forbid anyone else to use, share and improve\r
+ what you give them. Help stamp out software-hoarding!\r
+-------------------------------------------------------------------------*/\r
+#ifndef REG_ADUC84X_H\r
+#define REG_ADUC84X_H\r
+\r
+#include <compiler.h>\r
+\r
+SFR(CFG841, 0xAF); // ADuC841 Configuration SFR.\r
+SFR(CFG842, 0xAF); // ADuC842/ADuC843 Configuration SFR.\r
+ //For the two SFRs above these are the bits. Warning: some are different for\r
+ //the ADuC841 and ADuC842/ADuC843. Check the datasheet!\r
+ #define EPM2 0x10 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 2.\r
+ #define EPM1 0x08 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 1.\r
+ #define EPM0 0x04 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 0.\r
+ #define EXSP 0x80 // Extended SP Enable.\r
+ #define PWPO 0x40 // PWM Pin Out Selection.\r
+ #define DBUF 0x20 // DAC Output Buffer.\r
+ #define EXTCLK 0x10 // Set by the user to 1 to select an external clock input on P3.4.\r
+ #define MSPI 0x02 // Set to 1 by the user to move the SPI functionality of.\r
+ #define XRAMEN 0x01 // XRAM Enable Bit.\r
+\r
+SFR(SP, 0x81); // Stack Pointer.\r
+SFR(SPH, 0xB7); // Stack pointer high.\r
+\r
+SFR(DPL, 0x82); // Data Pointer Low.\r
+SFR(DPH, 0x83); // Data Pointer High.\r
+SFR(DPP, 0x84); // Data Pointer Page Byte.\r
+SFR(DPCON, 0xA7); // Data Pointer Control SFR.\r
+\r
+SFR(PCON, 0x87); // Power Control.\r
+ #define SMOD 0x80 //Double UART Baud Rate.\r
+ #define SERIPD 0x40 //I2C/SPI Power-Down Interrupt Enable.\r
+ #define INT0PD 0x20 //INT0 Power-Down Interrupt Enable.\r
+ #define ALEOFF 0x10 //Disable ALE Output.\r
+ #define GF1 0x08 //General-Purpose Flag Bit.\r
+ #define GF0 0x04 //General-Purpose Flag Bit.\r
+ #define PD 0x02 //Power-Down Mode Enable.\r
+ #define IDL 0x01 //Idle Mode Enable.\r
+\r
+SFR(TCON, 0x88); // Timer/Counter Control.\r
+ SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.\r
+ SBIT(TR1, 0x88, 6); // Timer 1 run control flag.\r
+ SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.\r
+ SBIT(TR0, 0x88, 4); // Timer 0 run control flag.\r
+ SBIT(IE1, 0x88, 3); // Interrupt 1 flag.\r
+ SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.\r
+ SBIT(IE0, 0x88, 1); // Interrupt 0 flag.\r
+ SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.\r
+\r
+SFR(TMOD, 0x89); // Timer/Counter Mode Control.\r
+ #define GATE1 0x80 // External enable for timer 1.\r
+ #define C_T1 0x40 // Timer or counter select for timer 1.\r
+ #define M1_1 0x20 // Operation mode bit 1 for timer 1.\r
+ #define M0_1 0x10 // Operation mode bit 0 for timer 1.\r
+ #define GATE0 0x08 // External enable for timer 0.\r
+ #define C_T0 0x04 // Timer or counter select for timer 0.\r
+ #define M1_0 0x02 // Operation mode bit 1 for timer 0.\r
+ #define M0_0 0x01 // Operation mode bit 0 for timer 0.\r
+\r
+SFR(TL0, 0x8A); // Timer 0 LSB.\r
+SFR(TL1, 0x8B); // Timer 1 LSB.\r
+SFR(TH0, 0x8C); // Timer 0 MSB.\r
+SFR(TH1, 0x8D); // Timer 1 MSB.\r
+\r
+SFR(P0, 0x80); // Port 0\r
+ SBIT(P0_0, 0x80, 0); // Port 0 bit 0.\r
+ SBIT(P0_1, 0x80, 1); // Port 0 bit 1.\r
+ SBIT(P0_2, 0x80, 2); // Port 0 bit 2.\r
+ SBIT(P0_3, 0x80, 3); // Port 0 bit 3.\r
+ SBIT(P0_4, 0x80, 4); // Port 0 bit 4.\r
+ SBIT(P0_5, 0x80, 5); // Port 0 bit 5.\r
+ SBIT(P0_6, 0x80, 6); // Port 0 bit 6.\r
+ SBIT(P0_7, 0x80, 7); // Port 0 bit 7.\r
+\r
+SFR(P1, 0x90); // Port 1\r
+ SBIT(P1_0, 0x90, 0); // Port 1 bit 0.\r
+ SBIT(P1_1, 0x90, 1); // Port 1 bit 1.\r
+ SBIT(P1_2, 0x90, 2); // Port 1 bit 2.\r
+ SBIT(P1_3, 0x90, 3); // Port 1 bit 3.\r
+ SBIT(P1_4, 0x90, 4); // Port 1 bit 4.\r
+ SBIT(P1_5, 0x90, 5); // Port 1 bit 5.\r
+ SBIT(P1_6, 0x90, 6); // Port 1 bit 6.\r
+ SBIT(P1_7, 0x90, 7); // Port 1 bit 7.\r
+ // Alternate names\r
+ SBIT(T2EX, 0x90, 1); //Capture/reload trigger for Counter 2.\r
+ SBIT(T2, 0x90, 0); //Input to Timer/Counter 2.\r
+\r
+SFR(P2, 0xA0); // Port 2\r
+ SBIT(P2_0, 0xA0, 0); // Port 2 bit 0.\r
+ SBIT(P2_1, 0xA0, 1); // Port 2 bit 1.\r
+ SBIT(P2_2, 0xA0, 2); // Port 2 bit 2.\r
+ SBIT(P2_3, 0xA0, 3); // Port 2 bit 3.\r
+ SBIT(P2_4, 0xA0, 4); // Port 2 bit 4.\r
+ SBIT(P2_5, 0xA0, 5); // Port 2 bit 5.\r
+ SBIT(P2_6, 0xA0, 6); // Port 2 bit 6.\r
+ SBIT(P2_7, 0xA0, 7); // Port 2 bit 7.\r
+\r
+SFR(P3, 0xB0); // Port 3\r
+ SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.\r
+ SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.\r
+ SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.\r
+ SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.\r
+ SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.\r
+ SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.\r
+ SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.\r
+ SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.\r
+ // Alternate names.\r
+ SBIT(RXD, 0xB0, 0);\r
+ SBIT(TXD, 0xB0, 1);\r
+ SBIT(INT0, 0xB0, 2);\r
+ SBIT(INT1, 0xB0, 3);\r
+ SBIT(T0, 0xB0, 4);\r
+ SBIT(T1, 0xB0, 5);\r
+ SBIT(WR, 0xB0, 6);\r
+ SBIT(RD, 0xB0, 7);\r
+\r
+SFR(I2CADD, 0x9B); // I2C Address Register 1.\r
+SFR(I2CADD1, 0x91); // I2C Address Register 2.\r
+SFR(I2CADD2, 0x92); // I2C Address Register 3.\r
+SFR(I2CADD3, 0x93); // I2C Address Register 4.\r
+SFR(I2CDAT, 0x9A); // I2C Data Register.\r
+\r
+SFR(SCON, 0x98); // Serial Port Control.\r
+ SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.\r
+ SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.\r
+ SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.\r
+ SBIT(REN, 0x98, 4); // Enables serial reception.\r
+ SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.\r
+ SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.\r
+ SBIT(TI, 0x98, 1); // Transmit interrupt flag.\r
+ SBIT(RI, 0x98, 0); // Receive interrupt flag.\r
+\r
+SFR(SBUF, 0x99); // Serial Data Buffer.\r
+\r
+//For these two, you may want to check page 68 of the datasheet...\r
+SFR(T3FD, 0x9D); // Fractional divider ratio.\r
+SFR(T3CON, 0x9E); // T3CON is the baud rate control SFR, allowing Timer 3 to be\r
+ // used to set up the UART baud rate, and setting up the binary\r
+ // divider (DIV).\r
+#define T3BAUDEN 0x80 // T3 UART BAUD Enable.\r
+#define DIV2 0x04 // Binary Divider Factor bit 3.\r
+#define DIV1 0x02 // Binary Divider Factor bit 2.\r
+#define DIV0 0x01 // Binary Divider Factor bit 1.\r
+\r
+SFR(TIMECON, 0xA1); // TIC Control Register.\r
+ #define TFH 0x40 // Twenty-Four Hour Select Bit.\r
+ #define ITS1 0x20 // Interval Timebase Selection Bit 1.\r
+ #define ITS0 0x10 // Interval Timebase Selection Bit 1.\r
+ #define STI 0x08 // Single Time Interval Bit.\r
+ #define TII 0x04 // TIC Interrupt Bit.\r
+ #define TIEN 0x02 // Time Interval Enable Bit.\r
+ #define TCEN 0x01 // Time Clock Enable Bit.\r
+\r
+SFR(HTHSEC, 0xA2); // Hundredths Seconds Time Register.\r
+SFR(SEC, 0xA3); // Seconds Time Register.\r
+SFR(MIN, 0xA4); // Minutes Time Register.\r
+SFR(HOUR, 0xA5); // Hours Time Register.\r
+SFR(INTVAL, 0xA6); // User Time Interval Select Register.\r
+\r
+SFR(IE, 0xA8); // Interrupt Enable.\r
+ SBIT(EA, 0xA8, 7); // Global Interrupt Enable.\r
+ SBIT(EADC, 0xA8, 6); // ADC Interrupt Enable.\r
+ SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable.\r
+ SBIT(ES, 0xA8, 4); // Serial Interrupt Enable.\r
+ SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable.\r
+ SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable.\r
+ SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable.\r
+ SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable.\r
+\r
+SFR(IEIP2, 0xA9); // Secondary Interrupt Enable Register\r
+ #define PTI 0x40 // Priority for time interval interrupt.\r
+ #define PPSM 0x20 // Priority for power supply monitor interrupt.\r
+ #define PSI2 0x10 // Priority for SPI/I2C interrupt. Same name as bit in IP???\r
+ #define ETI 0x04 // Enable time interval counter interrupts.\r
+ #define EPSMI 0x02 // Enable power supply monitor interrupts.\r
+ #define ESI 0x01 // Enable SPI or I2C serial port interrupts.\r
+\r
+SFR(PWMCON, 0xAE); //PWM control.\r
+ #define SNGL 0x80 // Turns off PMW output at P2.6 or P3.4.\r
+ #define MD2 0x40 // PWM Mode Bit 2.\r
+ #define MD1 0x20 // PWM Mode Bit 2.\r
+ #define MD0 0x10 // PWM Mode Bit 2.\r
+ #define CDIV1 0x08 // PWM Clock Divider bit 1.\r
+ #define CDIV0 0x04 // PWM Clock Divider bit 1.\r
+ #define CSEL1 0x02 // PWM Clock Select bit 1. (Typo in datasheet???)\r
+ #define CSEL0 0x01 // PWM Clock Select bit 0.\r
+\r
+SFR(PWM0L, 0xB1); // PWM 0 duty cycle low.\r
+SFR(PWM0H, 0xB2); // PWM 0 duty cycle high.\r
+SFR(PWM1L, 0xB3); // PWM 1 duty cycle low.\r
+SFR(PWM1H, 0xB4); // PWM 1 duty cycle high.\r
+\r
+SFR(IP, 0xB8); // Interrupt Priority Reg.\r
+ SBIT(PSI, 0xB8, 7); // Priority for SPI/I2C interrupt.\r
+ SBIT(PADC, 0xB8, 6); // ADC interrupt priority bit.\r
+ SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit.\r
+ SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit.\r
+ SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit.\r
+ SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit.\r
+ SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit.\r
+ SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit.\r
+\r
+SFR(ECON, 0xB9); // Flash/EE Memory Control SFR.\r
+SFR(EDATA1, 0xBC); // EE page data byte 1.\r
+SFR(EDATA2, 0xBD); // EE page data byte 2.\r
+SFR(EDATA3, 0xBE); // EE page data byte 3.\r
+SFR(EDATA4, 0xBF); // EE page data byte 4.\r
+SFR(EADRL, 0xC6); // EE address low.\r
+SFR(EADRH, 0xC7); // EE address high.\r
+\r
+SFR(WDCON, 0xC0); //Watchdog Timer Control Register.\r
+ SBIT(PRE3, 0xc0, 7); // Timeout period bit 4.\r
+ SBIT(PRE2, 0xc0, 6); // Timeout period bit 3.\r
+ SBIT(PRE1, 0xc0, 5); // Timeout period bit 2.\r
+ SBIT(PRE0, 0xc0, 4); // Timeout period bit 1.\r
+ SBIT(WDIR, 0xc0, 3); // Watchdog Interrupt Response Enable Bit.\r
+ SBIT(WDS, 0xc0, 2); // Watchdog Status Bit.\r
+ SBIT(WDE, 0xc0, 1); // Watchdog Enable Bit.\r
+ SBIT(WDWR, 0xc0, 0); // Watchdog Write Enable Bit.\r
+\r
+SFR(CHIPID, 0xC2); // System Self-Identification? WARNING: No description in the datasheet.\r
+\r
+SFR(T2CON, 0xC8); // Timer / Counter 2 Control.\r
+ SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag.\r
+ SBIT(EXF2, 0xC8, 6); // Timer 2 external flag.\r
+ SBIT(RCLK, 0xC8, 5); // Receive clock flag.\r
+ SBIT(TCLK, 0xC8, 4); // Transmit clock flag.\r
+ SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.\r
+ SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2.\r
+ SBIT(CNT2, 0xC8, 1); // Timer or coutner select.\r
+ SBIT(CAP2, 0xC8, 0); // Capture/reload flag.\r
+\r
+SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.\r
+SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.\r
+SFR(TL2, 0xCC); // Timer 2 LSB.\r
+SFR(TH2, 0xCD); // Timer 2 MSB.\r
+\r
+SFR(PSW, 0xD0); // Program Status Word.\r
+ SBIT(CY, 0xD0, 7); // Carry Flag.\r
+ SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag.\r
+ SBIT(F0, 0xD0, 5); // User-Defined Flag.\r
+ SBIT(RS1, 0xD0, 4); // Register Bank Select 1.\r
+ SBIT(RS0, 0xD0, 3); // Register Bank Select 0.\r
+ SBIT(OV, 0xD0, 2); // Overflow Flag.\r
+ SBIT(F1, 0xD0, 1); // User-Defined Flag.\r
+ SBIT(P, 0xD0, 0); // Parity Flag.\r
+\r
+SFR(DMAL, 0xD2); // DMA mode address pointer low.\r
+SFR(DMAH, 0xD3); // DMA mode address pointer high.\r
+SFR(DMAP, 0xD4); // DMA mode address pointer page. (?)\r
+SFR(PLLCON, 0xD7); // PLL Control Register.\r
+\r
+SFR(PSMCON, 0xDF); // Power supply monitor.\r
+ #define CMPD 0x40 // DVDD Comparator Bit.\r
+ #define PSMI 0x20 // Power Supply Monitor Interrupt Bit.\r
+ #define TPD1 0x10 // DVDD Trip Point Selection Bit 2.\r
+ #define TPD0 0x08 // DVDD Trip Point Selection Bit 1.\r
+ #define PSMEN 0x01 // Power Supply Monitor Enable Bit.\r
+\r
+SFR(ACC, 0xE0); // Accumulator\r
+ SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.\r
+ SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.\r
+ SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.\r
+ SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.\r
+ SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.\r
+ SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.\r
+ SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.\r
+ SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.\r
+\r
+SFR(I2CCON, 0xE8); // I2C Control Register\r
+ // Master mode\r
+ SBIT(MDO, 0xE8, 7); // I2C Software Master Data Output Bit.\r
+ SBIT(MDE, 0xE8, 6); // I2C Software Master Data Output Enable Bit.\r
+ SBIT(MCO, 0xE8, 5); // I2C Software Master Clock Output Bit.\r
+ SBIT(MDI, 0xE8, 4); // I2C Software Master Data Input Bit.\r
+ // Slave mode\r
+ SBIT(I2CSI, 0xE8, 7); // I2C Stop Interrupt Enable Bit.\r
+ SBIT(I2CGC, 0xE8, 6); // I2C General Call Status Bit.\r
+ SBIT(I2CID1, 0xE8, 5); // I2C Interrupt Decode Bit 2.\r
+ SBIT(I2CID0, 0xE8, 4); // I2C Interrupt Decode Bit 1.\r
+ SBIT(I2CM, 0xE8, 3); // I2C Master/Slave Mode Bit.\r
+ SBIT(I2CRS, 0xE8, 2); // I2C Reset Bit.\r
+ SBIT(I2CTX, 0xE8, 1); // I2C Direction Transfer Bit.\r
+ SBIT(I2CI, 0xE8, 0); // I2C Interrupt Bit.\r
+\r
+SFR(B, 0xF0); // B Register\r
+ SBIT(B_0, 0xF0, 0); // Register B bit 0.\r
+ SBIT(B_1, 0xF0, 1); // Register B bit 1.\r
+ SBIT(B_2, 0xF0, 2); // Register B bit 2.\r
+ SBIT(B_3, 0xF0, 3); // Register B bit 3.\r
+ SBIT(B_4, 0xF0, 4); // Register B bit 4.\r
+ SBIT(B_5, 0xF0, 5); // Register B bit 5.\r
+ SBIT(B_6, 0xF0, 6); // Register B bit 6.\r
+ SBIT(B_7, 0xF0, 7); // Register B bit 7.\r
+\r
+SFR(ADCCON1, 0xEF); //ADC Control SFR 1\r
+ //WARNING: bit 7 is named MD1 in the datasheet, but that name is already used.\r
+ #define MD 0x80 // The mode bit selects the active operating mode of the ADC.\r
+ #define EXT_REF 0x40 // Set by the user to select an external reference.\r
+ #define CK1 0x20 // The ADC clock divide bit 1.\r
+ #define CK0 0x10 // The ADC clock divide bit 0.\r
+ #define AQ1 0x08 // ADC acquisition select bit 1.\r
+ #define AQ0 0x04 // ADC acquisition select bit 0.\r
+ #define T2C 0x02 // The Timer 2 conversion bit.\r
+ #define EXC 0x01 // The external trigger enable bit.\r
+\r
+SFR(ADCCON2, 0xD8); // ADC Control SFR 2.\r
+ SBIT(ADCI, 0xD8, 7); // ADC Interrupt Bit.\r
+ SBIT(DMA, 0xD8, 6); // DMA Mode Enable Bit.\r
+ SBIT(CCONV, 0xD8, 5); // Continuous Conversion Bit.\r
+ SBIT(SCONV, 0xD8, 4); // Single Conversion Bit.\r
+ SBIT(CS3, 0xD8, 3); // Channel Selection Bit 4.\r
+ SBIT(CS2, 0xD8, 2); // Channel Selection Bit 3.\r
+ SBIT(CS1, 0xD8, 1); // Channel Selection Bit 2.\r
+ SBIT(CS0, 0xD8, 0); // Channel Selection Bit 1.\r
+\r
+SFR(ADCCON3, 0xF5); //ADC Control SFR 3\r
+ #define BUSY 0x80 // ADC Busy Status Bit.\r
+ #define AVGS1 0x20 // Number of Average Selection Bit 2.\r
+ #define AVGS0 0x10 // Number of Average Selection Bit 1.\r
+ #define TYPICAL 0x02 // Calibration Type Select Bit.\r
+ #define SCAL 0x01 // Start Calibration Cycle Bit.\r
+\r
+SFR(ADCDATAL, 0xD9); // ADC Result byte low.\r
+SFR(ADCDATAH, 0xDA); // ADC Result byte high. WARNING: bits 4 to 7 are the ADC channel!\r
+SFR(ADCOFSL, 0xF1); // Offset calibration coefficient byte (low).\r
+SFR(ADCOFSH, 0xF2); // Offset calibration coefficient byte (high).\r
+SFR(ADCGAINL, 0xF3); // Gain calibration coefficient byte (low).\r
+SFR(ADCGAINH, 0xF4); // Gain calibration coefficient byte (high).\r
+\r
+SFR(SPIDAT, 0xF7); // SPI Data Register.\r
+\r
+SFR(SPICON, 0xF8); // SPI Control Register.\r
+ SBIT(ISPI, 0xF8, 7); // SPI Interrupt Bit.\r
+ SBIT(WCOL, 0xF8, 6); // Write Collision Error Bit.\r
+ SBIT(SPE, 0xF8, 5); // SPI Interface Enable Bit.\r
+ SBIT(SPIM, 0xF8, 4); // SPI Master/Slave Mode Select Bit.\r
+ SBIT(CPOL, 0xF8, 3); // Clock Polarity Select Bit.\r
+ SBIT(CPHA, 0xF8, 2); // Clock Phase Select Bit.\r
+ SBIT(SPR1, 0xF8, 1); // SPI Bit Rate Select Bit 2.\r
+ SBIT(SPR0, 0xF8, 0); // SPI Bit Rate Select Bit 1.\r
+\r
+SFR(DAC0L, 0xF9); // DAC0 Data Low Byte.\r
+SFR(DAC0H, 0xFA); // DAC0 Data High Byte.\r
+SFR(DAC1L, 0xFB); // DAC1 Data Low Byte.\r
+SFR(DAC1H, 0xFC); // DAC1 Data High Byte.\r
+SFR(DACCON, 0xFD); // DAC Control Register.\r
+ #define MODE 0x80 // 8/12 bit selection.\r
+ #define RNG1 0x40 // DAC1 Range Select Bit.\r
+ #define RNG0 0x20 // DAC0 Range Select Bit.\r
+ #define CLR1 0x10 // DAC1 Clear Bit.\r
+ #define CLR0 0x08 // DAC0 Clear Bit.\r
+ #define SYNC 0x04 // DAC0/1 Update Synchronization Bit.\r
+ #define PD1 0x02 // DAC1 Power-Down Bit.\r
+ #define PD0 0x01 // DAC0 Power-Down Bit.\r
+\r
+#endif //REG_ADUC84X_H\r
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