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git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4898
4a8a32a2-be11-0410-ad9d-
d568d2c75423
+2007-08-09 Jesus Calvino-Fraga <jesusc at ece.ubc.ca>
+
+ * device/include/mcs51/at89c51ed.h: Fixed typo in declarations of CKCON0
+ and CKCON1.
+
2007-08-07 Erik Petrich <epetrich AT ivorytower.norman.ok.us>
* sdccconf_in.h: update the endian test so that SPARC Solaris
2007-08-07 Erik Petrich <epetrich AT ivorytower.norman.ok.us>
* sdccconf_in.h: update the endian test so that SPARC Solaris
#define DPS 0x01 //Data pointer select.
__sfr __at (0x97) CKRL; //Clock Reload Register
#define DPS 0x01 //Data pointer select.
__sfr __at (0x97) CKRL; //Clock Reload Register
-__sfr __at (0x8F) CKCKON0; //Clock control Register 0
+__sfr __at (0x8F) CKCON0; //Clock control Register 0
#define WDTX2 0x40 //Watch Dog Clock speed '1'=12 ck/cy, '0'=6 ck/cy
#define PCAX2 0x20 //Programmable Counter Array Clock speed '1'=12 ck/cy, '0'=6 ck/cy
#define SIX2 0x10 //Enhanced UART Clock (Mode 0 and 2) speed '1'=12 ck/cy, '0'=6 ck/cy
#define WDTX2 0x40 //Watch Dog Clock speed '1'=12 ck/cy, '0'=6 ck/cy
#define PCAX2 0x20 //Programmable Counter Array Clock speed '1'=12 ck/cy, '0'=6 ck/cy
#define SIX2 0x10 //Enhanced UART Clock (Mode 0 and 2) speed '1'=12 ck/cy, '0'=6 ck/cy
#define T1X2 0x04 //Timer1 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
#define T0X2 0x02 //Timer0 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
#define X2 0x01 //CPU Clock '0'=12 ck/cy, '1'=6 ck/cy
#define T1X2 0x04 //Timer1 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
#define T0X2 0x02 //Timer0 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
#define X2 0x01 //CPU Clock '0'=12 ck/cy, '1'=6 ck/cy
-__sfr __at (0x8F) CKCKON1; //Clock control Register 1
+__sfr __at (0x8F) CKCON1; //Clock control Register 1
#define XPIX2 0x01 //SPI Clock speed '1'=12 ck/cy, '0'=6 ck/cy
__sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH.
#define XPIX2 0x01 //SPI Clock speed '1'=12 ck/cy, '0'=6 ck/cy
__sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH.