made a new block ram based fifo, 64 (65) elements long, all fifos now have "enhanced...
authorMatt Ettus <matt@ettus.com>
Thu, 3 Sep 2009 17:37:35 +0000 (10:37 -0700)
committerMatt Ettus <matt@ettus.com>
Thu, 3 Sep 2009 17:37:35 +0000 (10:37 -0700)
commit4fff2505ffd0779126d8a2036d63f1fcc53bdb52
treeba53d8541f38ee4df3882800d4b0d2c9404d8f26
parent77dc1a9ba4ce9940d974edef8711d3eba85c0608
made a new block ram based fifo, 64 (65) elements long, all fifos now have "enhanced level logic" for accurate fullness.  Maybe this will help...
28 files changed:
usrp2/fpga/.gitignore [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.asy
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.ngc
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.sym
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.v
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.veo
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vhd
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vho
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.xco
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.ngc
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.v
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.xco
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.ngc [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.v [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.veo [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.xco [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_flist.txt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_readme.txt [new file with mode: 0644]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl [new file with mode: 0644]