X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm%2Fstm32l.h;h=6610f11dd18743752dd99c25b8517202ef73e109;hb=5b3a457f232e39977a437fc52256fc15c612b377;hp=0dbfae39814c0fd4a5e43805bbbe66c120800ce9;hpb=9b978cd467f9128f3069765dd8fbf8abad3459a4;p=fw%2Faltos diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h index 0dbfae39..6610f11d 100644 --- a/src/stm/stm32l.h +++ b/src/stm/stm32l.h @@ -3,7 +3,8 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of @@ -39,7 +40,7 @@ struct stm_gpio { }; #define STM_MODER_SHIFT(pin) ((pin) << 1) -#define STM_MODER_MASK 3 +#define STM_MODER_MASK 3UL #define STM_MODER_INPUT 0 #define STM_MODER_OUTPUT 1 #define STM_MODER_ALTERNATE 2 @@ -48,53 +49,87 @@ struct stm_gpio { static inline void stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) { gpio->moder = ((gpio->moder & - ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) | + (uint32_t) ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) | value << STM_MODER_SHIFT(pin)); } - -static inline vuint32_t + +static inline uint32_t +stm_spread_mask(uint16_t mask) { + uint32_t m = mask; + + /* 0000000000000000mmmmmmmmmmmmmmmm */ + m = (m & 0xff) | ((m & 0xff00) << 8); + /* 00000000mmmmmmmm00000000mmmmmmmm */ + m = (m & 0x000f000f) | ((m & 0x00f000f0) << 4); + /* 0000mmmm0000mmmm0000mmmm0000mmmm */ + m = (m & 0x03030303) | ((m & 0x0c0c0c0c) << 2); + /* 00mm00mm00mm00mm00mm00mm00mm00mm */ + m = (m & 0x11111111) | ((m & 0x22222222) << 2); + /* 0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m */ + return m; +} + +static inline void +stm_moder_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) { + uint32_t bits32 = stm_spread_mask(mask); + uint32_t mask32 = 3 * bits32; + uint32_t value32 = (value & 3) * bits32; + + gpio->moder = ((gpio->moder & ~mask32) | value32); +} + +static inline uint32_t stm_moder_get(struct stm_gpio *gpio, int pin) { return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK; } #define STM_OTYPER_SHIFT(pin) (pin) -#define STM_OTYPER_MASK 1 +#define STM_OTYPER_MASK 1UL #define STM_OTYPER_PUSH_PULL 0 #define STM_OTYPER_OPEN_DRAIN 1 static inline void stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) { gpio->otyper = ((gpio->otyper & - ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) | + (uint32_t) ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) | value << STM_OTYPER_SHIFT(pin)); } - -static inline vuint32_t + +static inline uint32_t stm_otyper_get(struct stm_gpio *gpio, int pin) { return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK; } #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1) -#define STM_OSPEEDR_MASK 3 +#define STM_OSPEEDR_MASK 3UL #define STM_OSPEEDR_400kHz 0 #define STM_OSPEEDR_2MHz 1 #define STM_OSPEEDR_10MHz 2 #define STM_OSPEEDR_40MHz 3 static inline void -stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) { +stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) { gpio->ospeedr = ((gpio->ospeedr & - ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) | + (uint32_t) ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) | value << STM_OSPEEDR_SHIFT(pin)); } - -static inline vuint32_t + +static inline void +stm_ospeedr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) { + uint32_t bits32 = stm_spread_mask(mask); + uint32_t mask32 = 3 * bits32; + uint32_t value32 = (value & 3) * bits32; + + gpio->ospeedr = ((gpio->ospeedr & ~mask32) | value32); +} + +static inline uint32_t stm_ospeedr_get(struct stm_gpio *gpio, int pin) { return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK; } #define STM_PUPDR_SHIFT(pin) ((pin) << 1) -#define STM_PUPDR_MASK 3 +#define STM_PUPDR_MASK 3UL #define STM_PUPDR_NONE 0 #define STM_PUPDR_PULL_UP 1 #define STM_PUPDR_PULL_DOWN 2 @@ -103,17 +138,26 @@ stm_ospeedr_get(struct stm_gpio *gpio, int pin) { static inline void stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) { gpio->pupdr = ((gpio->pupdr & - ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) | + (uint32_t) ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) | value << STM_PUPDR_SHIFT(pin)); } - + +static inline void +stm_pupdr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) { + uint32_t bits32 = stm_spread_mask(mask); + uint32_t mask32 = 3 * bits32; + uint32_t value32 = (value & 3) * bits32; + + gpio->pupdr = (gpio->pupdr & ~mask32) | value32; +} + static inline uint32_t stm_pupdr_get(struct stm_gpio *gpio, int pin) { return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK; } #define STM_AFR_SHIFT(pin) ((pin) << 2) -#define STM_AFR_MASK 0xf +#define STM_AFR_MASK 0xfUL #define STM_AFR_NONE 0 #define STM_AFR_AF0 0x0 #define STM_AFR_AF1 0x1 @@ -140,12 +184,12 @@ stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) { stm_moder_set(gpio, pin, STM_MODER_ALTERNATE); if (pin < 8) gpio->afrl = ((gpio->afrl & - ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | + (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | value << STM_AFR_SHIFT(pin)); else { pin -= 8; gpio->afrh = ((gpio->afrh & - ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | + (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | value << STM_AFR_SHIFT(pin)); } } @@ -166,11 +210,39 @@ stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) { gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin); } +static inline void +stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) { + /* Use the bit set/reset register to do this atomically */ + gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask)); +} + +static inline void +stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) { + gpio->bsrr = bits; +} + +static inline void +stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) { + gpio->bsrr = ((uint32_t) bits) << 16; +} + static inline uint8_t stm_gpio_get(struct stm_gpio *gpio, int pin) { return (gpio->idr >> pin) & 1; } +static inline uint16_t +stm_gpio_get_all(struct stm_gpio *gpio) { + return (uint16_t) gpio->idr; +} + +/* + * We can't define these in registers.ld or our fancy + * ao_enable_gpio macro will expand into a huge pile of code + * as the compiler won't do correct constant folding and + * dead-code elimination + */ + extern struct stm_gpio stm_gpioa; extern struct stm_gpio stm_gpiob; extern struct stm_gpio stm_gpioc; @@ -178,6 +250,13 @@ extern struct stm_gpio stm_gpiod; extern struct stm_gpio stm_gpioe; extern struct stm_gpio stm_gpioh; +#define stm_gpioh (*((struct stm_gpio *) 0x40021400)) +#define stm_gpioe (*((struct stm_gpio *) 0x40021000)) +#define stm_gpiod (*((struct stm_gpio *) 0x40020c00)) +#define stm_gpioc (*((struct stm_gpio *) 0x40020800)) +#define stm_gpiob (*((struct stm_gpio *) 0x40020400)) +#define stm_gpioa (*((struct stm_gpio *) 0x40020000)) + struct stm_usart { vuint32_t sr; /* status register */ vuint32_t dr; /* data register */ @@ -222,7 +301,7 @@ extern struct stm_usart stm_usart3; #define STM_USART_CR2_LINEN (14) /* LIN mode enable */ #define STM_USART_CR2_STOP (12) /* STOP bits */ -#define STM_USART_CR2_STOP_MASK 3 +#define STM_USART_CR2_STOP_MASK 3UL #define STM_USART_CR2_STOP_1 0 #define STM_USART_CR2_STOP_0_5 1 #define STM_USART_CR2_STOP_2 2 @@ -235,7 +314,7 @@ extern struct stm_usart stm_usart3; #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */ #define STM_USART_CR2_LBDL (5) /* lin break detection length */ #define STM_USART_CR2_ADD (0) -#define STM_USART_CR2_ADD_MASK 0xf +#define STM_USART_CR2_ADD_MASK 0xfUL #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */ #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */ @@ -286,7 +365,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_CR1_CKD_1 0 #define STM_TIM1011_CR1_CKD_2 1 #define STM_TIM1011_CR1_CKD_4 2 -#define STM_TIM1011_CR1_CKD_MASK 3 +#define STM_TIM1011_CR1_CKD_MASK 3UL #define STM_TIM1011_CR1_ARPE 7 #define STM_TIM1011_CR1_URS 2 #define STM_TIM1011_CR1_UDIS 1 @@ -299,7 +378,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_SMCR_ETPS_2 1 #define STM_TIM1011_SMCR_ETPS_4 2 #define STM_TIM1011_SMCR_ETPS_8 3 -#define STM_TIM1011_SMCR_ETPS_MASK 3 +#define STM_TIM1011_SMCR_ETPS_MASK 3UL #define STM_TIM1011_SMCR_ETF 8 #define STM_TIM1011_SMCR_ETF_NONE 0 #define STM_TIM1011_SMCR_ETF_CK_INT_2 1 @@ -317,7 +396,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_SMCR_ETF_DTS_32_5 13 #define STM_TIM1011_SMCR_ETF_DTS_32_6 14 #define STM_TIM1011_SMCR_ETF_DTS_32_8 15 -#define STM_TIM1011_SMCR_ETF_MASK 15 +#define STM_TIM1011_SMCR_ETF_MASK 15UL #define STM_TIM1011_DIER_CC1E 1 #define STM_TIM1011_DIER_UIE 0 @@ -339,7 +418,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7 -#define STM_TIM1011_CCMR1_OC1M_MASK 7 +#define STM_TIM1011_CCMR1_OC1M_MASK 7UL #define STM_TIM1011_CCMR1_OC1PE 3 #define STM_TIM1011_CCMR1_OC1FE 2 #define STM_TIM1011_CCMR1_CC1S 0 @@ -347,7 +426,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2 #define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3 -#define STM_TIM1011_CCMR1_CC1S_MASK 3 +#define STM_TIM1011_CCMR1_CC1S_MASK 3UL #define STM_TIM1011_CCMR1_IC1F_NONE 0 #define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1 @@ -365,13 +444,13 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13 #define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14 #define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15 -#define STM_TIM1011_CCMR1_IC1F_MASK 15 +#define STM_TIM1011_CCMR1_IC1F_MASK 15UL #define STM_TIM1011_CCMR1_IC1PSC 2 #define STM_TIM1011_CCMR1_IC1PSC_1 0 #define STM_TIM1011_CCMR1_IC1PSC_2 1 #define STM_TIM1011_CCMR1_IC1PSC_4 2 #define STM_TIM1011_CCMR1_IC1PSC_8 3 -#define STM_TIM1011_CCMR1_IC1PSC_MASK 3 +#define STM_TIM1011_CCMR1_IC1PSC_MASK 3UL #define STM_TIM1011_CCMR1_CC1S 0 #define STM_TIM1011_CCER_CC1NP 3 @@ -385,7 +464,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_TI1_RMP_LSI 1 #define STM_TIM1011_TI1_RMP_LSE 2 #define STM_TIM1011_TI1_RMP_RTC 3 -#define STM_TIM1011_TI1_RMP_MASK 3 +#define STM_TIM1011_TI1_RMP_MASK 3UL /* Flash interface */ @@ -435,6 +514,9 @@ extern struct stm_flash stm_flash; #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF #define STM_FLASH_PEKEYR_PEKEY2 0x02030405 +#define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF +#define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516 + struct stm_rcc { vuint32_t cr; vuint32_t icscr; @@ -465,7 +547,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3 -#define STM_RCC_CR_RTCPRE_HSE_MASK 3 +#define STM_RCC_CR_RTCPRE_HSE_MASK 3UL #define STM_RCC_CR_CSSON (28) #define STM_RCC_CR_PLLRDY (25) @@ -484,7 +566,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_MCOPRE_DIV_4 2 #define STM_RCC_CFGR_MCOPRE_DIV_8 3 #define STM_RCC_CFGR_MCOPRE_DIV_16 4 -#define STM_RCC_CFGR_MCOPRE_DIV_MASK 7 +#define STM_RCC_CFGR_MCOPRE_MASK 7UL #define STM_RCC_CFGR_MCOSEL (24) #define STM_RCC_CFGR_MCOSEL_DISABLE 0 @@ -495,13 +577,13 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_MCOSEL_PLL 5 #define STM_RCC_CFGR_MCOSEL_LSI 6 #define STM_RCC_CFGR_MCOSEL_LSE 7 -#define STM_RCC_CFGR_MCOSEL_MASK 7 +#define STM_RCC_CFGR_MCOSEL_MASK 7UL #define STM_RCC_CFGR_PLLDIV (22) #define STM_RCC_CFGR_PLLDIV_2 1 #define STM_RCC_CFGR_PLLDIV_3 2 #define STM_RCC_CFGR_PLLDIV_4 3 -#define STM_RCC_CFGR_PLLDIV_MASK 3 +#define STM_RCC_CFGR_PLLDIV_MASK 3UL #define STM_RCC_CFGR_PLLMUL (18) #define STM_RCC_CFGR_PLLMUL_3 0 @@ -513,7 +595,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_PLLMUL_24 6 #define STM_RCC_CFGR_PLLMUL_32 7 #define STM_RCC_CFGR_PLLMUL_48 8 -#define STM_RCC_CFGR_PLLMUL_MASK 0xf +#define STM_RCC_CFGR_PLLMUL_MASK 0xfUL #define STM_RCC_CFGR_PLLSRC (16) @@ -523,7 +605,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_PPRE2_DIV_4 5 #define STM_RCC_CFGR_PPRE2_DIV_8 6 #define STM_RCC_CFGR_PPRE2_DIV_16 7 -#define STM_RCC_CFGR_PPRE2_MASK 7 +#define STM_RCC_CFGR_PPRE2_MASK 7UL #define STM_RCC_CFGR_PPRE1 (8) #define STM_RCC_CFGR_PPRE1_DIV_1 0 @@ -531,7 +613,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_PPRE1_DIV_4 5 #define STM_RCC_CFGR_PPRE1_DIV_8 6 #define STM_RCC_CFGR_PPRE1_DIV_16 7 -#define STM_RCC_CFGR_PPRE1_MASK 7 +#define STM_RCC_CFGR_PPRE1_MASK 7UL #define STM_RCC_CFGR_HPRE (4) #define STM_RCC_CFGR_HPRE_DIV_1 0 @@ -543,21 +625,21 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_HPRE_DIV_128 0xd #define STM_RCC_CFGR_HPRE_DIV_256 0xe #define STM_RCC_CFGR_HPRE_DIV_512 0xf -#define STM_RCC_CFGR_HPRE_MASK 0xf +#define STM_RCC_CFGR_HPRE_MASK 0xfUL #define STM_RCC_CFGR_SWS (2) #define STM_RCC_CFGR_SWS_MSI 0 #define STM_RCC_CFGR_SWS_HSI 1 #define STM_RCC_CFGR_SWS_HSE 2 #define STM_RCC_CFGR_SWS_PLL 3 -#define STM_RCC_CFGR_SWS_MASK 3 +#define STM_RCC_CFGR_SWS_MASK 3UL #define STM_RCC_CFGR_SW (0) #define STM_RCC_CFGR_SW_MSI 0 #define STM_RCC_CFGR_SW_HSI 1 #define STM_RCC_CFGR_SW_HSE 2 #define STM_RCC_CFGR_SW_PLL 3 -#define STM_RCC_CFGR_SW_MASK 3 +#define STM_RCC_CFGR_SW_MASK 3UL #define STM_RCC_AHBENR_DMA1EN (24) #define STM_RCC_AHBENR_FLITFEN (15) @@ -610,7 +692,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CSR_RTCSEL_LSE 1 #define STM_RCC_CSR_RTCSEL_LSI 2 #define STM_RCC_CSR_RTCSEL_HSE 3 -#define STM_RCC_CSR_RTCSEL_MASK 3 +#define STM_RCC_CSR_RTCSEL_MASK 3UL #define STM_RCC_CSR_LSEBYP (10) #define STM_RCC_CSR_LSERDY (9) @@ -628,10 +710,10 @@ extern struct stm_pwr stm_pwr; #define STM_PWR_CR_LPRUN (14) #define STM_PWR_CR_VOS (11) -#define STM_PWR_CR_VOS_1_8 1 -#define STM_PWR_CR_VOS_1_5 2 -#define STM_PWR_CR_VOS_1_2 3 -#define STM_PWR_CR_VOS_MASK 3 +#define STM_PWR_CR_VOS_1_8 1UL +#define STM_PWR_CR_VOS_1_5 2UL +#define STM_PWR_CR_VOS_1_2 3UL +#define STM_PWR_CR_VOS_MASK 3UL #define STM_PWR_CR_FWU (10) #define STM_PWR_CR_ULP (9) @@ -646,7 +728,7 @@ extern struct stm_pwr stm_pwr; #define STM_PWR_CR_PLS_2_9 5 #define STM_PWR_CR_PLS_3_1 6 #define STM_PWR_CR_PLS_EXT 7 -#define STM_PWR_CR_PLS_MASK 7 +#define STM_PWR_CR_PLS_MASK 7UL #define STM_PWR_CR_PVDE (4) #define STM_PWR_CR_CSBF (3) @@ -693,7 +775,7 @@ extern struct stm_tim67 stm_tim6; #define STM_TIM67_CR2_MMS_RESET 0 #define STM_TIM67_CR2_MMS_ENABLE 1 #define STM_TIM67_CR2_MMS_UPDATE 2 -#define STM_TIM67_CR2_MMS_MASK 7 +#define STM_TIM67_CR2_MMS_MASK 7UL #define STM_TIM67_DIER_UDE (8) #define STM_TIM67_DIER_UIE (0) @@ -719,7 +801,7 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_CR_BIAS_1_4 0 #define STM_LCD_CR_BIAS_1_2 1 #define STM_LCD_CR_BIAS_1_3 2 -#define STM_LCD_CR_BIAS_MASK 3 +#define STM_LCD_CR_BIAS_MASK 3UL #define STM_LCD_CR_DUTY (2) #define STM_LCD_CR_DUTY_STATIC 0 @@ -727,7 +809,7 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_CR_DUTY_1_3 2 #define STM_LCD_CR_DUTY_1_4 3 #define STM_LCD_CR_DUTY_1_8 4 -#define STM_LCD_CR_DUTY_MASK 7 +#define STM_LCD_CR_DUTY_MASK 7UL #define STM_LCD_CR_VSEL (1) #define STM_LCD_CR_LCDEN (0) @@ -749,7 +831,7 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_FCR_PS_8192 0xd #define STM_LCD_FCR_PS_16384 0xe #define STM_LCD_FCR_PS_32768 0xf -#define STM_LCD_FCR_PS_MASK 0xf +#define STM_LCD_FCR_PS_MASK 0xfUL #define STM_LCD_FCR_DIV (18) #define STM_LCD_FCR_DIV_16 0x0 @@ -768,14 +850,14 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_FCR_DIV_29 0xd #define STM_LCD_FCR_DIV_30 0xe #define STM_LCD_FCR_DIV_31 0xf -#define STM_LCD_FCR_DIV_MASK 0xf +#define STM_LCD_FCR_DIV_MASK 0xfUL #define STM_LCD_FCR_BLINK (16) #define STM_LCD_FCR_BLINK_DISABLE 0 #define STM_LCD_FCR_BLINK_SEG0_COM0 1 #define STM_LCD_FCR_BLINK_SEG0_COMALL 2 #define STM_LCD_FCR_BLINK_SEGALL_COMALL 3 -#define STM_LCD_FCR_BLINK_MASK 3 +#define STM_LCD_FCR_BLINK_MASK 3UL #define STM_LCD_FCR_BLINKF (13) #define STM_LCD_FCR_BLINKF_8 0 @@ -786,16 +868,16 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_FCR_BLINKF_256 5 #define STM_LCD_FCR_BLINKF_512 6 #define STM_LCD_FCR_BLINKF_1024 7 -#define STM_LCD_FCR_BLINKF_MASK 7 +#define STM_LCD_FCR_BLINKF_MASK 7UL #define STM_LCD_FCR_CC (10) -#define STM_LCD_FCR_CC_MASK 7 +#define STM_LCD_FCR_CC_MASK 7UL #define STM_LCD_FCR_DEAD (7) -#define STM_LCD_FCR_DEAD_MASK 7 +#define STM_LCD_FCR_DEAD_MASK 7UL #define STM_LCD_FCR_PON (4) -#define STM_LCD_FCR_PON_MASK 7 +#define STM_LCD_FCR_PON_MASK 7UL #define STM_LCD_FCR_UDDIE (3) #define STM_LCD_FCR_SOFIE (1) @@ -811,30 +893,63 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_CLR_UDDC (3) #define STM_LCD_CLR_SOFC (1) +/* The SYSTICK starts at 0xe000e010 */ + +struct stm_systick { + vuint32_t csr; + vuint32_t rvr; + vuint32_t cvr; + vuint32_t calib; +}; + +extern struct stm_systick stm_systick; + +#define STM_SYSTICK_CSR_ENABLE 0 +#define STM_SYSTICK_CSR_TICKINT 1 +#define STM_SYSTICK_CSR_CLKSOURCE 2 +#define STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 0 +#define STM_SYSTICK_CSR_CLKSOURCE_HCLK 1 +#define STM_SYSTICK_CSR_COUNTFLAG 16 + +/* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */ + struct stm_nvic { - vuint32_t iser[3]; /* 0x000 */ + vuint32_t iser[8]; /* 0x000 0xe000e100 Set Enable Register */ + + uint8_t _unused020[0x080 - 0x020]; - uint8_t _unused00c[0x080 - 0x00c]; + vuint32_t icer[8]; /* 0x080 0xe000e180 Clear Enable Register */ - vuint32_t icer[3]; /* 0x080 */ + uint8_t _unused0a0[0x100 - 0x0a0]; - uint8_t _unused08c[0x100 - 0x08c]; + vuint32_t ispr[8]; /* 0x100 0xe000e200 Set Pending Register */ - vuint32_t ispr[3]; /* 0x100 */ + uint8_t _unused120[0x180 - 0x120]; - uint8_t _unused10c[0x180 - 0x10c]; + vuint32_t icpr[8]; /* 0x180 0xe000e280 Clear Pending Register */ - vuint32_t icpr[3]; /* 0x180 */ + uint8_t _unused1a0[0x200 - 0x1a0]; - uint8_t _unused18c[0x200 - 0x18c]; + vuint32_t iabr[8]; /* 0x200 0xe000e300 Active Bit Register */ - vuint32_t iabr[3]; /* 0x200 */ + uint8_t _unused220[0x300 - 0x220]; - uint8_t _unused20c[0x300 - 0x20c]; + vuint32_t ipr[60]; /* 0x300 0xe000e400 Priority Register */ - vuint32_t ipr[21]; /* 0x300 */ + uint8_t _unused3f0[0xc00 - 0x3f0]; - uint8_t _unused324[0xe00 - 0x324]; + vuint32_t cpuid_base; /* 0xc00 0xe000ed00 CPUID Base Register */ + vuint32_t ics; /* 0xc04 0xe000ed04 Interrupt Control State Register */ + vuint32_t vto; /* 0xc08 0xe000ed08 Vector Table Offset Register */ + vuint32_t ai_rc; /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */ + vuint32_t sc; /* 0xc10 0xe000ed10 System Control Register */ + vuint32_t cc; /* 0xc14 0xe000ed14 Configuration Control Register */ + + vuint32_t shpr7_4; /* 0xc18 0xe000ed18 System Hander Priority Registers */ + vuint32_t shpr11_8; /* 0xc1c */ + vuint32_t shpr15_12; /* 0xc20 */ + + uint8_t _unusedc18[0xe00 - 0xc24]; vuint32_t stir; /* 0xe00 */ }; @@ -891,7 +1006,7 @@ stm_nvic_set_priority(int irq, uint8_t prio) { uint32_t v; v = stm_nvic.ipr[n]; - v &= ~IRQ_PRIO_MASK(irq); + v &= (uint32_t) ~IRQ_PRIO_MASK(irq); v |= (prio) << IRQ_PRIO_BIT(irq); stm_nvic.ipr[n] = v; } @@ -949,9 +1064,9 @@ struct stm_mpu { extern struct stm_mpu stm_mpu; #define STM_MPU_TYPER_IREGION 16 -#define STM_MPU_TYPER_IREGION_MASK 0xff +#define STM_MPU_TYPER_IREGION_MASK 0xffUL #define STM_MPU_TYPER_DREGION 8 -#define STM_MPU_TYPER_DREGION_MASK 0xff +#define STM_MPU_TYPER_DREGION_MASK 0xffUL #define STM_MPU_TYPER_SEPARATE 0 #define STM_MPU_CR_PRIVDEFENA 2 @@ -959,14 +1074,14 @@ extern struct stm_mpu stm_mpu; #define STM_MPU_CR_ENABLE 0 #define STM_MPU_RNR_REGION 0 -#define STM_MPU_RNR_REGION_MASK 0xff +#define STM_MPU_RNR_REGION_MASK 0xffUL #define STM_MPU_RBAR_ADDR 5 -#define STM_MPU_RBAR_ADDR_MASK 0x7ffffff +#define STM_MPU_RBAR_ADDR_MASK 0x7ffffffUL #define STM_MPU_RBAR_VALID 4 #define STM_MPU_RBAR_REGION 0 -#define STM_MPU_RBAR_REGION_MASK 0xf +#define STM_MPU_RBAR_REGION_MASK 0xfUL #define STM_MPU_RASR_XN 28 #define STM_MPU_RASR_AP 24 @@ -976,76 +1091,79 @@ extern struct stm_mpu stm_mpu; #define STM_MPU_RASR_AP_RW_RW 3 #define STM_MPU_RASR_AP_RO_NONE 5 #define STM_MPU_RASR_AP_RO_RO 6 -#define STM_MPU_RASR_AP_MASK 7 +#define STM_MPU_RASR_AP_MASK 7UL #define STM_MPU_RASR_TEX 19 -#define STM_MPU_RASR_TEX_MASK 7 +#define STM_MPU_RASR_TEX_MASK 7UL #define STM_MPU_RASR_S 18 #define STM_MPU_RASR_C 17 #define STM_MPU_RASR_B 16 #define STM_MPU_RASR_SRD 8 -#define STM_MPU_RASR_SRD_MASK 0xff +#define STM_MPU_RASR_SRD_MASK 0xffUL #define STM_MPU_RASR_SIZE 1 -#define STM_MPU_RASR_SIZE_MASK 0x1f +#define STM_MPU_RASR_SIZE_MASK 0x1fUL #define STM_MPU_RASR_ENABLE 0 -#define isr(name) void stm_ ## name ## _isr(void); - -isr(nmi) -isr(hardfault) -isr(memmanage) -isr(busfault) -isr(usagefault) -isr(svc) -isr(debugmon) -isr(pendsv) -isr(systick) -isr(wwdg) -isr(pvd) -isr(tamper_stamp) -isr(rtc_wkup) -isr(flash) -isr(rcc) -isr(exti0) -isr(exti1) -isr(exti2) -isr(exti3) -isr(exti4) -isr(dma1_channel1) -isr(dma1_channel2) -isr(dma1_channel3) -isr(dma1_channel4) -isr(dma1_channel5) -isr(dma1_channel6) -isr(dma1_channel7) -isr(adc1) -isr(usb_hp) -isr(usb_lp) -isr(dac) -isr(comp) -isr(exti9_5) -isr(lcd) -isr(tim9) -isr(tim10) -isr(tim11) -isr(tim2) -isr(tim3) -isr(tim4) -isr(i2c1_ev) -isr(i2c1_er) -isr(i2c2_ev) -isr(i2c2_er) -isr(spi1) -isr(spi2) -isr(usart1) -isr(usart2) -isr(usart3) -isr(exti15_10) -isr(rtc_alarm) -isr(usb_fs_wkup) -isr(tim6) -isr(tim7) - -#undef isr +#define isr_decl(name) void stm_ ## name ## _isr(void) + +isr_decl(halt); +isr_decl(ignore); + +isr_decl(nmi); +isr_decl(hardfault); +isr_decl(memmanage); +isr_decl(busfault); +isr_decl(usagefault); +isr_decl(svc); +isr_decl(debugmon); +isr_decl(pendsv); +isr_decl(systick); +isr_decl(wwdg); +isr_decl(pvd); +isr_decl(tamper_stamp); +isr_decl(rtc_wkup); +isr_decl(flash); +isr_decl(rcc); +isr_decl(exti0); +isr_decl(exti1); +isr_decl(exti2); +isr_decl(exti3); +isr_decl(exti4); +isr_decl(dma1_channel1); +isr_decl(dma1_channel2); +isr_decl(dma1_channel3); +isr_decl(dma1_channel4); +isr_decl(dma1_channel5); +isr_decl(dma1_channel6); +isr_decl(dma1_channel7); +isr_decl(adc1); +isr_decl(usb_hp); +isr_decl(usb_lp); +isr_decl(dac); +isr_decl(comp); +isr_decl(exti9_5); +isr_decl(lcd); +isr_decl(tim9); +isr_decl(tim10); +isr_decl(tim11); +isr_decl(tim2); +isr_decl(tim3); +isr_decl(tim4); +isr_decl(i2c1_ev); +isr_decl(i2c1_er); +isr_decl(i2c2_ev); +isr_decl(i2c2_er); +isr_decl(spi1); +isr_decl(spi2); +isr_decl(usart1); +isr_decl(usart2); +isr_decl(usart3); +isr_decl(exti15_10); +isr_decl(rtc_alarm); +isr_decl(usb_fs_wkup); +isr_decl(tim6); +isr_decl(tim7); + +#undef isr_decl #define STM_ISR_WWDG_POS 0 #define STM_ISR_PVD_POS 1 @@ -1105,7 +1223,7 @@ extern struct stm_syscfg stm_syscfg; #define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0 #define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1 #define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3 -#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3 +#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3UL #define STM_SYSCFG_PMC_USB_PU 0 @@ -1118,7 +1236,7 @@ extern struct stm_syscfg stm_syscfg; static inline void stm_exticr_set(struct stm_gpio *gpio, int pin) { - uint8_t reg = pin >> 2; + uint8_t reg = (uint8_t) (pin >> 2); uint8_t shift = (pin & 3) << 2; uint8_t val = 0; @@ -1136,7 +1254,7 @@ stm_exticr_set(struct stm_gpio *gpio, int pin) { else if (gpio == &stm_gpioe) val = STM_SYSCFG_EXTICR_PE; - stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift; + stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & (uint32_t) ~(0xf << shift)) | val << shift; } @@ -1164,14 +1282,14 @@ extern struct stm_dma stm_dma; #define STM_DMA_INDEX(channel) ((channel) - 1) #define STM_DMA_ISR(index) ((index) << 2) -#define STM_DMA_ISR_MASK 0xf +#define STM_DMA_ISR_MASK 0xfUL #define STM_DMA_ISR_TEIF 3 #define STM_DMA_ISR_HTIF 2 #define STM_DMA_ISR_TCIF 1 #define STM_DMA_ISR_GIF 0 #define STM_DMA_IFCR(index) ((index) << 2) -#define STM_DMA_IFCR_MASK 0xf +#define STM_DMA_IFCR_MASK 0xfUL #define STM_DMA_IFCR_CTEIF 3 #define STM_DMA_IFCR_CHTIF 2 #define STM_DMA_IFCR_CTCIF 1 @@ -1284,7 +1402,7 @@ extern struct stm_spi stm_spi1, stm_spi2, stm_spi3; #define STM_SPI_CR1_BR_PCLK_64 5 #define STM_SPI_CR1_BR_PCLK_128 6 #define STM_SPI_CR1_BR_PCLK_256 7 -#define STM_SPI_CR1_BR_MASK 7 +#define STM_SPI_CR1_BR_MASK 7UL #define STM_SPI_CR1_MSTR 2 #define STM_SPI_CR1_CPOL 1 @@ -1297,10 +1415,13 @@ extern struct stm_spi stm_spi1, stm_spi2, stm_spi3; #define STM_SPI_CR2_TXDMAEN 1 #define STM_SPI_CR2_RXDMAEN 0 +#define STM_SPI_SR_FRE 8 #define STM_SPI_SR_BSY 7 #define STM_SPI_SR_OVR 6 #define STM_SPI_SR_MODF 5 #define STM_SPI_SR_CRCERR 4 +#define STM_SPI_SR_UDR 3 +#define STM_SPI_SR_CHSIDE 2 #define STM_SPI_SR_TXE 1 #define STM_SPI_SR_RXNE 0 @@ -1335,6 +1456,9 @@ struct stm_adc { extern struct stm_adc stm_adc; +#define STM_ADC_SQ_TEMP 16 +#define STM_ADC_SQ_V_REF 17 + #define STM_ADC_SR_JCNR 9 #define STM_ADC_SR_RCNR 8 #define STM_ADC_SR_ADONS 6 @@ -1351,7 +1475,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR1_RES_10 1 #define STM_ADC_CR1_RES_8 2 #define STM_ADC_CR1_RES_6 3 -#define STM_ADC_CR1_RES_MASK 3 +#define STM_ADC_CR1_RES_MASK 3UL #define STM_ADC_CR1_AWDEN 23 #define STM_ADC_CR1_JAWDEN 22 #define STM_ADC_CR1_PDI 17 @@ -1365,7 +1489,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR1_DISCNUM_6 5 #define STM_ADC_CR1_DISCNUM_7 6 #define STM_ADC_CR1_DISCNUM_8 7 -#define STM_ADC_CR1_DISCNUM_MASK 7 +#define STM_ADC_CR1_DISCNUM_MASK 7UL #define STM_ADC_CR1_JDISCEN 12 #define STM_ADC_CR1_DISCEN 11 #define STM_ADC_CR1_JAUTO 10 @@ -1375,7 +1499,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR1_AWDIE 6 #define STM_ADC_CR1_EOCIE 5 #define STM_ADC_CR1_AWDCH 0 -#define STM_ADC_CR1_AWDCH_MASK 0x1f +#define STM_ADC_CR1_AWDCH_MASK 0x1fUL #define STM_ADC_CR2_SWSTART 30 #define STM_ADC_CR2_EXTEN 28 @@ -1383,7 +1507,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR2_EXTEN_RISING 1 #define STM_ADC_CR2_EXTEN_FALLING 2 #define STM_ADC_CR2_EXTEN_BOTH 3 -#define STM_ADC_CR2_EXTEN_MASK 3 +#define STM_ADC_CR2_EXTEN_MASK 3UL #define STM_ADC_CR2_EXTSEL 24 #define STM_ADC_CR2_EXTSEL_TIM9_CC2 0 #define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1 @@ -1397,14 +1521,14 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9 #define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10 #define STM_ADC_CR2_EXTSEL_EXTI_11 15 -#define STM_ADC_CR2_EXTSEL_MASK 15 +#define STM_ADC_CR2_EXTSEL_MASK 15UL #define STM_ADC_CR2_JWSTART 22 #define STM_ADC_CR2_JEXTEN 20 #define STM_ADC_CR2_JEXTEN_DISABLE 0 #define STM_ADC_CR2_JEXTEN_RISING 1 #define STM_ADC_CR2_JEXTEN_FALLING 2 #define STM_ADC_CR2_JEXTEN_BOTH 3 -#define STM_ADC_CR2_JEXTEN_MASK 3 +#define STM_ADC_CR2_JEXTEN_MASK 3UL #define STM_ADC_CR2_JEXTSEL 16 #define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0 #define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1 @@ -1418,7 +1542,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9 #define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10 #define STM_ADC_CR2_JEXTSEL_EXTI_15 15 -#define STM_ADC_CR2_JEXTSEL_MASK 15 +#define STM_ADC_CR2_JEXTSEL_MASK 15UL #define STM_ADC_CR2_ALIGN 11 #define STM_ADC_CR2_EOCS 10 #define STM_ADC_CR2_DDS 9 @@ -1432,7 +1556,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR2_DELS_63 5 #define STM_ADC_CR2_DELS_127 6 #define STM_ADC_CR2_DELS_255 7 -#define STM_ADC_CR2_DELS_MASK 7 +#define STM_ADC_CR2_DELS_MASK 7UL #define STM_ADC_CR2_CONT 1 #define STM_ADC_CR2_ADON 0 @@ -1441,7 +1565,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CCR_ADCPRE_HSI_1 0 #define STM_ADC_CCR_ADCPRE_HSI_2 1 #define STM_ADC_CCR_ADCPRE_HSI_4 2 -#define STM_ADC_CCR_ADCPRE_MASK 3 +#define STM_ADC_CCR_ADCPRE_MASK 3UL struct stm_temp_cal { uint16_t vref; @@ -1455,6 +1579,36 @@ extern struct stm_temp_cal stm_temp_cal; #define stm_temp_cal_cold 25 #define stm_temp_cal_hot 110 +struct stm_dbg_mcu { + uint32_t idcode; +}; + +extern struct stm_dbg_mcu stm_dbg_mcu; + +static inline uint16_t +stm_dev_id(void) { + return stm_dbg_mcu.idcode & 0xfff; +} + +struct stm_flash_size { + uint16_t f_size; +}; + +extern struct stm_flash_size stm_flash_size_medium; +extern struct stm_flash_size stm_flash_size_large; + +/* Returns flash size in bytes */ +extern uint32_t +stm_flash_size(void); + +struct stm_device_id { + uint32_t u_id0; + uint32_t u_id1; + uint32_t u_id2; +}; + +extern struct stm_device_id stm_device_id; + #define STM_NUM_I2C 2 #define STM_I2C_INDEX(channel) ((channel) - 1) @@ -1498,8 +1652,9 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_CR2_FREQ_4_MHZ 4 #define STM_I2C_CR2_FREQ_8_MHZ 8 #define STM_I2C_CR2_FREQ_16_MHZ 16 +#define STM_I2C_CR2_FREQ_24_MHZ 24 #define STM_I2C_CR2_FREQ_32_MHZ 32 -#define STM_I2C_CR2_FREQ_MASK 0x3f +#define STM_I2C_CR2_FREQ_MASK 0x3fUL #define STM_I2C_SR1_SMBALERT 15 #define STM_I2C_SR1_TIMEOUT 14 @@ -1517,7 +1672,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_SR1_SB 0 #define STM_I2C_SR2_PEC 8 -#define STM_I2C_SR2_PEC_MASK 0xff00 +#define STM_I2C_SR2_PEC_MASK 0xff00UL #define STM_I2C_SR2_DUALF 7 #define STM_I2C_SR2_SMBHOST 6 #define STM_I2C_SR2_SMBDEFAULT 5 @@ -1529,7 +1684,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_CCR_FS 15 #define STM_I2C_CCR_DUTY 14 #define STM_I2C_CCR_CCR 0 -#define STM_I2C_CCR_MASK 0x7ff +#define STM_I2C_CCR_MASK 0x7ffUL struct stm_tim234 { vuint32_t cr1; @@ -1566,14 +1721,14 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CR1_CKD_1 0 #define STM_TIM234_CR1_CKD_2 1 #define STM_TIM234_CR1_CKD_4 2 -#define STM_TIM234_CR1_CKD_MASK 3 +#define STM_TIM234_CR1_CKD_MASK 3UL #define STM_TIM234_CR1_ARPE 7 #define STM_TIM234_CR1_CMS 5 #define STM_TIM234_CR1_CMS_EDGE 0 #define STM_TIM234_CR1_CMS_CENTER_1 1 #define STM_TIM234_CR1_CMS_CENTER_2 2 #define STM_TIM234_CR1_CMS_CENTER_3 3 -#define STM_TIM234_CR1_CMS_MASK 3 +#define STM_TIM234_CR1_CMS_MASK 3UL #define STM_TIM234_CR1_DIR 4 #define STM_TIM234_CR1_DIR_UP 0 #define STM_TIM234_CR1_DIR_DOWN 1 @@ -1592,7 +1747,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5 #define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6 #define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7 -#define STM_TIM234_CR2_MMS_MASK 7 +#define STM_TIM234_CR2_MMS_MASK 7UL #define STM_TIM234_CR2_CCDS 3 #define STM_TIM234_SMCR_ETP 15 @@ -1602,7 +1757,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_SMCR_ETPS_DIV_2 1 #define STM_TIM234_SMCR_ETPS_DIV_4 2 #define STM_TIM234_SMCR_ETPS_DIV_8 3 -#define STM_TIM234_SMCR_ETPS_MASK 3 +#define STM_TIM234_SMCR_ETPS_MASK 3UL #define STM_TIM234_SMCR_ETF 8 #define STM_TIM234_SMCR_ETF_NONE 0 #define STM_TIM234_SMCR_ETF_INT_N_2 1 @@ -1620,7 +1775,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_SMCR_ETF_DTS_32_N_5 13 #define STM_TIM234_SMCR_ETF_DTS_32_N_6 14 #define STM_TIM234_SMCR_ETF_DTS_32_N_8 15 -#define STM_TIM234_SMCR_ETF_MASK 15 +#define STM_TIM234_SMCR_ETF_MASK 15UL #define STM_TIM234_SMCR_MSM 7 #define STM_TIM234_SMCR_TS 4 #define STM_TIM234_SMCR_TS_ITR0 0 @@ -1631,7 +1786,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_SMCR_TS_TI1FP1 5 #define STM_TIM234_SMCR_TS_TI2FP2 6 #define STM_TIM234_SMCR_TS_ETRF 7 -#define STM_TIM234_SMCR_TS_MASK 7 +#define STM_TIM234_SMCR_TS_MASK 7UL #define STM_TIM234_SMCR_OCCS 3 #define STM_TIM234_SMCR_SMS 0 #define STM_TIM234_SMCR_SMS_DISABLE 0 @@ -1642,7 +1797,21 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_SMCR_SMS_GATED_MODE 5 #define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6 #define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7 -#define STM_TIM234_SMCR_SMS_MASK 7 +#define STM_TIM234_SMCR_SMS_MASK 7UL + +#define STM_TIM234_DIER_TDE 14 +#define STM_TIM234_DIER_CC4DE 12 +#define STM_TIM234_DIER_CC3DE 11 +#define STM_TIM234_DIER_CC2DE 10 +#define STM_TIM234_DIER_CC1DE 9 +#define STM_TIM234_DIER_UDE 8 + +#define STM_TIM234_DIER_TIE 6 +#define STM_TIM234_DIER_CC4IE 4 +#define STM_TIM234_DIER_CC3IE 3 +#define STM_TIM234_DIER_CC2IE 2 +#define STM_TIM234_DIER_CC1IE 1 +#define STM_TIM234_DIER_UIE 0 #define STM_TIM234_SR_CC4OF 12 #define STM_TIM234_SR_CC3OF 11 @@ -1672,7 +1841,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7 -#define STM_TIM234_CCMR1_OC2M_MASK 7 +#define STM_TIM234_CCMR1_OC2M_MASK 7UL #define STM_TIM234_CCMR1_OC2PE 11 #define STM_TIM234_CCMR1_OC2FE 10 #define STM_TIM234_CCMR1_CC2S 8 @@ -1680,7 +1849,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1 #define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2 #define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3 -#define STM_TIM234_CCMR1_CC2S_MASK 3 +#define STM_TIM234_CCMR1_CC2S_MASK 3UL #define STM_TIM234_CCMR1_OC1CE 7 #define STM_TIM234_CCMR1_OC1M 4 @@ -1692,17 +1861,62 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7 -#define STM_TIM234_CCMR1_OC1M_MASK 7 -#define STM_TIM234_CCMR1_OC1PE 11 +#define STM_TIM234_CCMR1_OC1M_MASK 7UL +#define STM_TIM234_CCMR1_OC1PE 3 #define STM_TIM234_CCMR1_OC1FE 2 #define STM_TIM234_CCMR1_CC1S 0 #define STM_TIM234_CCMR1_CC1S_OUTPUT 0 #define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1 #define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2 #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3 -#define STM_TIM234_CCMR1_CC1S_MASK 3 - -#define STM_TIM234_CCMR2_OC2CE 15 +#define STM_TIM234_CCMR1_CC1S_MASK 3UL + +#define STM_TIM234_CCMR1_IC2F 12 +#define STM_TIM234_CCMR1_IC2F_NONE 0 +#define STM_TIM234_CCMR1_IC2F_CK_INT_N_2 1 +#define STM_TIM234_CCMR1_IC2F_CK_INT_N_4 2 +#define STM_TIM234_CCMR1_IC2F_CK_INT_N_8 3 +#define STM_TIM234_CCMR1_IC2F_DTS_2_N_6 4 +#define STM_TIM234_CCMR1_IC2F_DTS_2_N_8 5 +#define STM_TIM234_CCMR1_IC2F_DTS_4_N_6 6 +#define STM_TIM234_CCMR1_IC2F_DTS_4_N_8 7 +#define STM_TIM234_CCMR1_IC2F_DTS_8_N_6 8 +#define STM_TIM234_CCMR1_IC2F_DTS_8_N_8 9 +#define STM_TIM234_CCMR1_IC2F_DTS_16_N_5 10 +#define STM_TIM234_CCMR1_IC2F_DTS_16_N_6 11 +#define STM_TIM234_CCMR1_IC2F_DTS_16_N_8 12 +#define STM_TIM234_CCMR1_IC2F_DTS_32_N_5 13 +#define STM_TIM234_CCMR1_IC2F_DTS_32_N_6 14 +#define STM_TIM234_CCMR1_IC2F_DTS_32_N_8 15 +#define STM_TIM234_CCMR1_IC2PSC 10 +#define STM_TIM234_CCMR1_IC2PSC_NONE 0 +#define STM_TIM234_CCMR1_IC2PSC_2 1 +#define STM_TIM234_CCMR1_IC2PSC_4 2 +#define STM_TIM234_CCMR1_IC2PSC_8 3 +#define STM_TIM234_CCMR1_IC1F 4 +#define STM_TIM234_CCMR1_IC1F_NONE 0 +#define STM_TIM234_CCMR1_IC1F_CK_INT_N_2 1 +#define STM_TIM234_CCMR1_IC1F_CK_INT_N_4 2 +#define STM_TIM234_CCMR1_IC1F_CK_INT_N_8 3 +#define STM_TIM234_CCMR1_IC1F_DTS_2_N_6 4 +#define STM_TIM234_CCMR1_IC1F_DTS_2_N_8 5 +#define STM_TIM234_CCMR1_IC1F_DTS_4_N_6 6 +#define STM_TIM234_CCMR1_IC1F_DTS_4_N_8 7 +#define STM_TIM234_CCMR1_IC1F_DTS_8_N_6 8 +#define STM_TIM234_CCMR1_IC1F_DTS_8_N_8 9 +#define STM_TIM234_CCMR1_IC1F_DTS_16_N_5 10 +#define STM_TIM234_CCMR1_IC1F_DTS_16_N_6 11 +#define STM_TIM234_CCMR1_IC1F_DTS_16_N_8 12 +#define STM_TIM234_CCMR1_IC1F_DTS_32_N_5 13 +#define STM_TIM234_CCMR1_IC1F_DTS_32_N_6 14 +#define STM_TIM234_CCMR1_IC1F_DTS_32_N_8 15 +#define STM_TIM234_CCMR1_IC1PSC 2 +#define STM_TIM234_CCMR1_IC1PSC_NONE 0 +#define STM_TIM234_CCMR1_IC1PSC_2 1 +#define STM_TIM234_CCMR1_IC1PSC_4 2 +#define STM_TIM234_CCMR1_IC1PSC_8 3 + +#define STM_TIM234_CCMR2_OC4CE 15 #define STM_TIM234_CCMR2_OC4M 12 #define STM_TIM234_CCMR2_OC4M_FROZEN 0 #define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1 @@ -1712,7 +1926,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7 -#define STM_TIM234_CCMR2_OC4M_MASK 7 +#define STM_TIM234_CCMR2_OC4M_MASK 7UL #define STM_TIM234_CCMR2_OC4PE 11 #define STM_TIM234_CCMR2_OC4FE 10 #define STM_TIM234_CCMR2_CC4S 8 @@ -1720,7 +1934,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1 #define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2 #define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3 -#define STM_TIM234_CCMR2_CC4S_MASK 3 +#define STM_TIM234_CCMR2_CC4S_MASK 3UL #define STM_TIM234_CCMR2_OC3CE 7 #define STM_TIM234_CCMR2_OC3M 4 @@ -1732,27 +1946,35 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7 -#define STM_TIM234_CCMR2_OC3M_MASK 7 -#define STM_TIM234_CCMR2_OC3PE 11 +#define STM_TIM234_CCMR2_OC3M_MASK 7UL +#define STM_TIM234_CCMR2_OC3PE 3 #define STM_TIM234_CCMR2_OC3FE 2 #define STM_TIM234_CCMR2_CC3S 0 #define STM_TIM234_CCMR2_CC3S_OUTPUT 0 #define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1 #define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2 #define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3 -#define STM_TIM234_CCMR2_CC3S_MASK 3 +#define STM_TIM234_CCMR2_CC3S_MASK 3UL #define STM_TIM234_CCER_CC4NP 15 #define STM_TIM234_CCER_CC4P 13 +#define STM_TIM234_CCER_CC4P_ACTIVE_HIGH 0 +#define STM_TIM234_CCER_CC4P_ACTIVE_LOW 1 #define STM_TIM234_CCER_CC4E 12 #define STM_TIM234_CCER_CC3NP 11 #define STM_TIM234_CCER_CC3P 9 +#define STM_TIM234_CCER_CC3P_ACTIVE_HIGH 0 +#define STM_TIM234_CCER_CC3P_ACTIVE_LOW 1 #define STM_TIM234_CCER_CC3E 8 #define STM_TIM234_CCER_CC2NP 7 #define STM_TIM234_CCER_CC2P 5 +#define STM_TIM234_CCER_CC2P_ACTIVE_HIGH 0 +#define STM_TIM234_CCER_CC2P_ACTIVE_LOW 1 #define STM_TIM234_CCER_CC2E 4 #define STM_TIM234_CCER_CC1NP 3 #define STM_TIM234_CCER_CC1P 1 +#define STM_TIM234_CCER_CC1P_ACTIVE_HIGH 0 +#define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1 #define STM_TIM234_CCER_CC1E 0 struct stm_usb { @@ -1774,7 +1996,7 @@ struct stm_usb { #define STM_USB_EPR_STAT_RX_STALL 1 #define STM_USB_EPR_STAT_RX_NAK 2 #define STM_USB_EPR_STAT_RX_VALID 3 -#define STM_USB_EPR_STAT_RX_MASK 3 +#define STM_USB_EPR_STAT_RX_MASK 3UL #define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0 #define STM_USB_EPR_SETUP 11 #define STM_USB_EPR_EP_TYPE 9 @@ -1782,7 +2004,7 @@ struct stm_usb { #define STM_USB_EPR_EP_TYPE_CONTROL 1 #define STM_USB_EPR_EP_TYPE_ISO 2 #define STM_USB_EPR_EP_TYPE_INTERRUPT 3 -#define STM_USB_EPR_EP_TYPE_MASK 3 +#define STM_USB_EPR_EP_TYPE_MASK 3UL #define STM_USB_EPR_EP_KIND 8 #define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */ #define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */ @@ -1796,9 +2018,9 @@ struct stm_usb { #define STM_USB_EPR_STAT_TX_NAK 2 #define STM_USB_EPR_STAT_TX_VALID 3 #define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0 -#define STM_USB_EPR_STAT_TX_MASK 3 +#define STM_USB_EPR_STAT_TX_MASK 3UL #define STM_USB_EPR_EA 0 -#define STM_USB_EPR_EA_MASK 0xf +#define STM_USB_EPR_EA_MASK 0xfUL #define STM_USB_CNTR_CTRM 15 #define STM_USB_CNTR_PMAOVRM 14 @@ -1824,19 +2046,19 @@ struct stm_usb { #define STM_USB_ISTR_ESOF 8 #define STM_USB_ISTR_DIR 4 #define STM_USB_ISTR_EP_ID 0 -#define STM_USB_ISTR_EP_ID_MASK 0xf +#define STM_USB_ISTR_EP_ID_MASK 0xfUL #define STM_USB_FNR_RXDP 15 #define STM_USB_FNR_RXDM 14 #define STM_USB_FNR_LCK 13 #define STM_USB_FNR_LSOF 11 -#define STM_USB_FNR_LSOF_MASK 0x3 +#define STM_USB_FNR_LSOF_MASK 0x3UL #define STM_USB_FNR_FN 0 -#define STM_USB_FNR_FN_MASK 0x7ff +#define STM_USB_FNR_FN_MASK 0x7ffUL #define STM_USB_DADDR_EF 7 #define STM_USB_DADDR_ADD 0 -#define STM_USB_DADDR_ADD_MASK 0x7f +#define STM_USB_DADDR_ADD_MASK 0x7fUL extern struct stm_usb stm_usb; @@ -1859,13 +2081,13 @@ union stm_usb_bdt { #define STM_USB_BDT_COUNT_RX_BL_SIZE 15 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10 -#define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1f +#define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1fUL #define STM_USB_BDT_COUNT_RX_COUNT_RX 0 -#define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ff +#define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ffUL #define STM_USB_BDT_SIZE 8 -extern uint8_t stm_usb_sram[]; +extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4))); struct stm_exti { vuint32_t imr;