X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm%2Fstm32l.h;h=54d95c9ac574edb80d406b9593d7f14c1ad69f62;hb=e9362841b1075a2ae59eecc73137b20e700567a8;hp=338bc4711f29b2f93fee150195cbecd3b7e013d0;hpb=0bce68e6a0abc19f49c573331164d13643c9bee5;p=fw%2Faltos

diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h
index 338bc471..54d95c9a 100644
--- a/src/stm/stm32l.h
+++ b/src/stm/stm32l.h
@@ -1164,4 +1164,80 @@ extern struct stm_temp_cal	stm_temp_cal;
 #define stm_temp_cal_cold	25
 #define stm_temp_cal_hot	110
 
+#define STM_NUM_I2C	2
+
+#define STM_I2C_INDEX(channel)	((channel) - 1)
+
+struct stm_i2c {
+	vuint32_t	cr1;
+	vuint32_t	cr2;
+	vuint32_t	oar1;
+	vuint32_t	oar2;
+	vuint32_t	dr;
+	vuint32_t	sr1;
+	vuint32_t	sr2;
+	vuint32_t	ccr;
+	vuint32_t	trise;
+};
+
+extern struct stm_i2c stm_i2c1, stm_i2c2;
+
+#define STM_I2C_CR1_SWRST	15
+#define STM_I2C_CR1_ALERT	13
+#define STM_I2C_CR1_PEC		12
+#define STM_I2C_CR1_POS		11
+#define STM_I2C_CR1_ACK		10
+#define STM_I2C_CR1_STOP	9
+#define STM_I2C_CR1_START	8
+#define STM_I2C_CR1_NOSTRETCH	7
+#define STM_I2C_CR1_ENGC	6
+#define STM_I2C_CR1_ENPEC	5
+#define STM_I2C_CR1_ENARP	4
+#define STM_I2C_CR1_SMBTYPE	3
+#define STM_I2C_CR1_SMBUS	1
+#define STM_I2C_CR1_PE		0
+
+#define STM_I2C_CR2_LAST	12
+#define STM_I2C_CR2_DMAEN	11
+#define STM_I2C_CR2_ITBUFEN	10
+#define STM_I2C_CR2_ITEVTEN	9
+#define STM_I2C_CR2_ITERREN	8
+#define STM_I2C_CR2_FREQ	0
+#define  STM_I2C_CR2_FREQ_2_MHZ		2
+#define  STM_I2C_CR2_FREQ_4_MHZ		4
+#define  STM_I2C_CR2_FREQ_8_MHZ		8
+#define  STM_I2C_CR2_FREQ_16_MHZ	16
+#define  STM_I2C_CR2_FREQ_32_MHZ	32
+#define  STM_I2C_CR2_FREQ_MASK		0x3f;
+
+#define STM_I2C_SR1_SMBALERT	15
+#define STM_I2C_SR1_TIMEOUT	14
+#define STM_I2C_SR1_PECERR	12
+#define STM_I2C_SR1_OVR		11
+#define STM_I2C_SR1_AF		10
+#define STM_I2C_SR1_ARLO	9
+#define STM_I2C_SR1_BERR	8
+#define STM_I2C_SR1_TXE		7
+#define STM_I2C_SR1_RXNE	6
+#define STM_I2C_SR1_STOPF	4
+#define STM_I2C_SR1_ADD10	3
+#define STM_I2C_SR1_BTF		2
+#define STM_I2C_SR1_ADDR	1
+#define STM_I2C_SR1_SB		0
+
+#define STM_I2C_SR2_PEC		8
+#define  STM_I2C_SR2_PEC_MASK	0xff00
+#define STM_I2C_SR2_DUALF	7
+#define STM_I2C_SR2_SMBHOST	6
+#define STM_I2C_SR2_SMBDEFAULT	5
+#define STM_I2C_SR2_GENCALL	4
+#define STM_I2C_SR2_TRA		2
+#define STM_I2C_SR2_BUSY       	1
+#define STM_I2C_SR2_MSL		0
+
+#define STM_I2C_CCR_FS		15
+#define STM_I2C_CCR_DUTY	14
+#define STM_I2C_CCR_CCR		0
+#define  STM_I2C_CCR_MASK	0x7ff
+
 #endif /* _STM32L_H_ */