X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm%2Fao_timer.c;h=481b81ef1142b244500f544bc46975594fddc091;hb=HEAD;hp=9e9436cfa685dae451ae27ff59b8c9af6b32be1c;hpb=0686a7b8aec524d81bda4c572549a3a068ce0eed;p=fw%2Faltos

diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c
index 9e9436cf..481b81ef 100644
--- a/src/stm/ao_timer.c
+++ b/src/stm/ao_timer.c
@@ -36,6 +36,23 @@ ao_time(void)
 {
 	return ao_tick_count;
 }
+
+uint64_t
+ao_time_ns(void)
+{
+	AO_TICK_TYPE	before, after;
+	uint32_t	cvr;
+
+	do {
+		before = ao_tick_count;
+		cvr = stm_systick.cvr;
+		after = ao_tick_count;
+	} while (before != after);
+
+	return (uint64_t) after * (1000000000ULL / AO_HERTZ) +
+		(uint64_t) cvr * (1000000000ULL / AO_SYSTICK);
+}
+
 #endif
 
 #if AO_DATA_ALL
@@ -50,12 +67,9 @@ void stm_systick_isr(void)
 #if HAS_TICK
 		++ao_tick_count;
 #endif
-#if HAS_TASK_QUEUE
-		if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
-			ao_task_check_alarm((uint16_t) ao_tick_count);
-#endif
+		ao_task_check_alarm();
 #if AO_DATA_ALL
-		if (++ao_data_count == ao_data_interval) {
+		if (++ao_data_count == ao_data_interval && ao_data_interval) {
 			ao_data_count = 0;
 #if HAS_FAKE_FLIGHT
 			if (ao_fake_flight_active)
@@ -95,7 +109,7 @@ ao_timer_init(void)
 	stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
 			   (1 << STM_SYSTICK_CSR_TICKINT) |
 			   (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
-	stm_nvic.shpr15_12 |= AO_STM_NVIC_CLOCK_PRIORITY << 24;
+	stm_nvic.shpr15_12 |= (uint32_t) AO_STM_NVIC_CLOCK_PRIORITY << 24;
 }
 
 #endif
@@ -111,7 +125,7 @@ ao_clock_init(void)
 	while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
 		ao_arch_nop();
 
-	stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
+	stm_rcc.cfgr = (stm_rcc.cfgr & ~(uint32_t) (STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
 		(STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW);
 
 	/* wait for system to switch to MSI */
@@ -135,7 +149,7 @@ ao_clock_init(void)
 #if AO_HSE_BYPASS
 	stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
 #else
-	stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
+	stm_rcc.cr &= ~(uint32_t) (1 << STM_RCC_CR_HSEBYP);
 #endif
 	/* Enable HSE clock */
 	stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
@@ -211,8 +225,8 @@ ao_clock_init(void)
 	stm_rcc.cfgr = cfgr;
 
 	/* Disable the PLL */
-	stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
-	while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
+	stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON);
+	while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
 		asm("nop");
 	
 	/* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
@@ -224,7 +238,7 @@ ao_clock_init(void)
 	cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
 
 	/* PLL source */
-	cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
+	cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC);
 	cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
 
 	stm_rcc.cfgr = cfgr;