fix problem I always have with cc1111 vias not having rational clearance

[hw/teleterra] / teleterra.pcb

diff --git a/teleterra.pcb b/teleterra.pcb
index 05d5e475a34376d1ec7f60956b9261d554d41eb5..c07857ddda89cb2476fd706e5a17852c3a0bdbcb 100644 (file)
--- a/teleterra.pcb
+++ b/teleterra.pcb
@@ -1362,15 +1362,15 @@ Element["" "KSCJ" "S3" "unknown" 242300 118900 6900 -2600 0 100 ""]
 
 Element["" "TI-QFN36" "U9" "CC1111" 287881 59780 -5919 -8878 0 100 ""]
 (
-       Pin[5919 -5919 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
-       Pin[5919 0 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
-       Pin[5919 5920 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
-       Pin[0 -5919 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
-       Pin[0 0 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
-       Pin[0 5920 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
-       Pin[-5920 -5919 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
-       Pin[-5920 0 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
-       Pin[-5920 5920 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
+       Pin[5919 -5919 2900 2500 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
+       Pin[5919 0 2900 2500 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
+       Pin[5919 5920 2900 2500 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
+       Pin[0 -5919 2900 2500 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
+       Pin[0 0 2900 2500 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
+       Pin[0 5920 2900 2500 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
+       Pin[-5920 -5919 2900 2500 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
+       Pin[-5920 0 2900 2500 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
+       Pin[-5920 5920 2900 2500 0 1500 "GND Exposed" "37" "via,thermal(1S)"]
        Pad[0 0 0 0 17323 0 0 "GND Exposed" "37" "square,edge2,nopaste"]
        Pad[5919 -5919 5919 -5919 2960 0 0 "GND Exposed" "37" "square,edge2,nopaste"]
        Pad[5919 -2959 5919 -2959 2960 0 2960 "GND Exposed" "37" "square,edge2,nopaste"]
@@ -2154,6 +2154,7 @@ Layer(2 "bottom")
 )
 Layer(3 "outline")
 (
+       Attribute("PCB::skip-drc" "1")
        Line[27550 0 342550 0 1000 2000 "lock"]
        Line[27550 175200 342550 175200 1000 2000 "lock"]
        Line[0 28550 0 146650 1000 2000 "lock"]