freedfm pointed out a number of soldermask relief violations, all around the

[hw/cncfpga] / Notebook

diff --git a/Notebook b/Notebook
index 654b43360e64486844b94ae9eef27ef5b09156a1..fc479e3c7ffaa11951eec193195e62bf223b6cd1 100644 (file)
--- a/Notebook
+++ b/Notebook
@@ -32,7 +32,7 @@ To Do:
        **DONE**
 
     db25 pin 11 to sole pin side of one "1L" transistor, one lead to ground, 
-    4.7k from remaining lead to pin 87
+    4.7k from remaining lead to pin 87, another 4.7k between pins 87 and 90
 
        db25 pin 11 is nWait .. so it looks like nWait is being driven by
        a transistor from the FPGA DEV_CLRn output, not directly
@@ -47,6 +47,18 @@ To Do:
 
        **DONE**
 
+    why not treat all the parallel port input pins with transistors?
+
+       http://emergent.unpythonic.net/01165081407 has an answer, that they
+       are used as inverters because the FPGA has weak pull-ups on those
+       pins yet those pins need to be driven low or the PC can't configure
+       the FPGA by "printing to it" .. apparently that only applies to the
+       two pins that have the inverters on them.
+
+       Duh.  Of course they're inverting... how'd I miss that?
+
+       **DONE**
+
     pin 49 hooked to pin 51 .. nCONFIG driven by nConfig
 
        **DONE**
@@ -57,31 +69,16 @@ To Do:
        **DONE**
 
     26 pin header pins 11 and 12 to sole pin side of "G1" transistor, both other
-    leads have caps to ground, one to pin 24, the other to pin 37, 35
-
-       those header pins are VCC?
-       pin 37, 35 is VCCIO
-       pin 24 is TMS
+    leads have caps to ground
 
-       WTF?
-
-       SOT-23 with G1 label could be:
-
-               transistor, 1=B, 2=E, 3(sole)=C
-               fet, 1=G, 2=S, 3=D
-
-       so:
-               TMS is driving base or gate
-               3.3V is on emitter or source
-               header VCC is on collector or drain
-
-       TMS is 'test mode state' on the jtag interface, which drives the TAP
-       controller state machine.  TMS going low starts a cycle?
+       if it's an NPN transistor:
+               emitter attached to VCCINT
+               base and collector both to VCCIO
+               VCCIO is driven by 3.3V regulator, VCCINT is not
 
     4.7k between pins 87 and 90
 
        pin 87 is DEV_CLRn driving nWait to the PC
-       pin 90 is CLOCK hooked to db25 pin 1 whcih is nWrite
 
-    why not treat all the parallel port input pins with transistors?
+       **DONE**