flesh out the .gitignore

[hw/cncfpga] / Notebook

diff --git a/Notebook b/Notebook
index 7ba2524129a68d920de81f86f39ab560216ea7aa..fc479e3c7ffaa11951eec193195e62bf223b6cd1 100644 (file)
--- a/Notebook
+++ b/Notebook
@@ -3,8 +3,82 @@ http://www.fourwalledcubicle.com/LUFA.php
 
 To Do:
 
-- figure out the nConfig / nCONFIG wiring by inspecting my real Pluto-P
 - figure out if all the unconnected pins on the FPGA match the Pluto-P
 
 - verify pin configuration seems to match the data in:
   ~/src/emc2-dev/src/hal/drivers/pluto_servo_firmware/pluto_servo.pin 
+
+
+2011.12.04
+- results of physical inspection of pluto-p board
+
+    22 ohm series resistors on 7 pins between FPGA and 10 pin header, including
+       pins 5, 8, 9, 10, 13, 16, 93
+
+       ** these are din_1 through din_7 .. makes sense?
+
+       **DONE**
+
+    pin 50 has an LED and 1k resistor
+
+       ** my current design has 330 ohms
+
+       **NOT DONE .. CAN CHANGE IF NEEDED AFTER PCB FAB**
+
+    10k from pin 25 to pin 44, cap from pin 44 to ground
+
+       44 is VCCIO, 25 is nSTATUS, so this is a pull-up on nSTATUS
+
+       **DONE**
+
+    db25 pin 11 to sole pin side of one "1L" transistor, one lead to ground, 
+    4.7k from remaining lead to pin 87, another 4.7k between pins 87 and 90
+
+       db25 pin 11 is nWait .. so it looks like nWait is being driven by
+       a transistor from the FPGA DEV_CLRn output, not directly
+
+       **DONE**
+
+    db25 pin 12 to sole pin side of one "1L" transistor, one lead to ground,
+    4.7k from remaining lead to pin 6
+
+       db25 pin 12 is undocumented?
+       so FPGA pin 6 is able to drive that pin through a transistor
+
+       **DONE**
+
+    why not treat all the parallel port input pins with transistors?
+
+       http://emergent.unpythonic.net/01165081407 has an answer, that they
+       are used as inverters because the FPGA has weak pull-ups on those
+       pins yet those pins need to be driven low or the PC can't configure
+       the FPGA by "printing to it" .. apparently that only applies to the
+       two pins that have the inverters on them.
+
+       Duh.  Of course they're inverting... how'd I miss that?
+
+       **DONE**
+
+    pin 49 hooked to pin 51 .. nCONFIG driven by nConfig
+
+       **DONE**
+
+    osc pin 3 to pin 91
+
+       consistent with my design, 40mhz to FPGA
+       **DONE**
+
+    26 pin header pins 11 and 12 to sole pin side of "G1" transistor, both other
+    leads have caps to ground
+
+       if it's an NPN transistor:
+               emitter attached to VCCINT
+               base and collector both to VCCIO
+               VCCIO is driven by 3.3V regulator, VCCINT is not
+
+    4.7k between pins 87 and 90
+
+       pin 87 is DEV_CLRn driving nWait to the PC
+
+       **DONE**
+