+ I have nWrite on pin 75, while the KNJN document says nWrite is parallel
+ port pin 1 and that should be on FPGA pin 90. The pluto_servo.pin file in
+ the EMC2 pluto-p driver directory seems to say that pin 75 is a bidir DCLK
+ signale, and pin 90 is an nWrite *input*. The parallel port doc says that
+ pin 1 is nStrobe in SPP mode and nWrite in EPP mode. In both cases, that
+ seems like a signal from the PC to the FPGA (strobing data in). Reading
+ the verilog source, nWrite is indeed an input to the FPGA and is used to
+ determine the EPP mode.