// megafunction wizard: %LPM_ADD_SUB%CBX% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: lpm_add_sub // ============================================================ // File Name: add32.v // Megafunction Name(s): // lpm_add_sub // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // ************************************************************ //Copyright (C) 1991-2003 Altera Corporation //Any megafunction design, and related netlist (encrypted or decrypted), //support information, device programming or simulation file, and any other //associated documentation or information provided by Altera or a partner //under Altera's Megafunction Partnership Program may be used only //to program PLD devices (but not masked PLD devices) from Altera. Any //other use of such megafunction design, netlist, support information, //device programming or simulation file, or any other related documentation //or information is prohibited for any other purpose, including, but not //limited to modification, reverse engineering, de-compiling, or use with //any other silicon devices, unless such use is explicitly licensed under //a separate agreement with Altera or a megafunction partner. Title to the //intellectual property, including patents, copyrights, trademarks, trade //secrets, or maskworks, embodied in any such megafunction design, netlist, //support information, device programming or simulation file, or any other //related documentation or information provided by Altera or a megafunction //partner, remains with Altera, the megafunction partner, or their respective //licensors. No other licenses, including any licenses needed under any third //party's intellectual property, are provided herein. //lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result //VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END //synthesis_resources = lut 8 module add32_add_sub_nq7 ( dataa, datab, result) /* synthesis synthesis_clearbox=1 */; input [7:0] dataa; input [7:0] datab; output [7:0] result; wire [7:0] wire_add_sub_cella_combout; wire [0:0] wire_add_sub_cella_0cout; wire [0:0] wire_add_sub_cella_1cout; wire [0:0] wire_add_sub_cella_2cout; wire [0:0] wire_add_sub_cella_3cout; wire [0:0] wire_add_sub_cella_4cout; wire [0:0] wire_add_sub_cella_5cout; wire [0:0] wire_add_sub_cella_6cout; wire [7:0] wire_add_sub_cella_dataa; wire [7:0] wire_add_sub_cella_datab; stratix_lcell add_sub_cella_0 ( .cin(1'b0), .combout(wire_add_sub_cella_combout[0:0]), .cout(wire_add_sub_cella_0cout[0:0]), .dataa(wire_add_sub_cella_dataa[0:0]), .datab(wire_add_sub_cella_datab[0:0])); defparam add_sub_cella_0.cin_used = "true", add_sub_cella_0.lut_mask = "96e8", add_sub_cella_0.operation_mode = "arithmetic", add_sub_cella_0.sum_lutc_input = "cin", add_sub_cella_0.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_1 ( .cin(wire_add_sub_cella_0cout[0:0]), .combout(wire_add_sub_cella_combout[1:1]), .cout(wire_add_sub_cella_1cout[0:0]), .dataa(wire_add_sub_cella_dataa[1:1]), .datab(wire_add_sub_cella_datab[1:1])); defparam add_sub_cella_1.cin_used = "true", add_sub_cella_1.lut_mask = "96e8", add_sub_cella_1.operation_mode = "arithmetic", add_sub_cella_1.sum_lutc_input = "cin", add_sub_cella_1.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_2 ( .cin(wire_add_sub_cella_1cout[0:0]), .combout(wire_add_sub_cella_combout[2:2]), .cout(wire_add_sub_cella_2cout[0:0]), .dataa(wire_add_sub_cella_dataa[2:2]), .datab(wire_add_sub_cella_datab[2:2])); defparam add_sub_cella_2.cin_used = "true", add_sub_cella_2.lut_mask = "96e8", add_sub_cella_2.operation_mode = "arithmetic", add_sub_cella_2.sum_lutc_input = "cin", add_sub_cella_2.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_3 ( .cin(wire_add_sub_cella_2cout[0:0]), .combout(wire_add_sub_cella_combout[3:3]), .cout(wire_add_sub_cella_3cout[0:0]), .dataa(wire_add_sub_cella_dataa[3:3]), .datab(wire_add_sub_cella_datab[3:3])); defparam add_sub_cella_3.cin_used = "true", add_sub_cella_3.lut_mask = "96e8", add_sub_cella_3.operation_mode = "arithmetic", add_sub_cella_3.sum_lutc_input = "cin", add_sub_cella_3.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_4 ( .cin(wire_add_sub_cella_3cout[0:0]), .combout(wire_add_sub_cella_combout[4:4]), .cout(wire_add_sub_cella_4cout[0:0]), .dataa(wire_add_sub_cella_dataa[4:4]), .datab(wire_add_sub_cella_datab[4:4])); defparam add_sub_cella_4.cin_used = "true", add_sub_cella_4.lut_mask = "96e8", add_sub_cella_4.operation_mode = "arithmetic", add_sub_cella_4.sum_lutc_input = "cin", add_sub_cella_4.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_5 ( .cin(wire_add_sub_cella_4cout[0:0]), .combout(wire_add_sub_cella_combout[5:5]), .cout(wire_add_sub_cella_5cout[0:0]), .dataa(wire_add_sub_cella_dataa[5:5]), .datab(wire_add_sub_cella_datab[5:5])); defparam add_sub_cella_5.cin_used = "true", add_sub_cella_5.lut_mask = "96e8", add_sub_cella_5.operation_mode = "arithmetic", add_sub_cella_5.sum_lutc_input = "cin", add_sub_cella_5.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_6 ( .cin(wire_add_sub_cella_5cout[0:0]), .combout(wire_add_sub_cella_combout[6:6]), .cout(wire_add_sub_cella_6cout[0:0]), .dataa(wire_add_sub_cella_dataa[6:6]), .datab(wire_add_sub_cella_datab[6:6])); defparam add_sub_cella_6.cin_used = "true", add_sub_cella_6.lut_mask = "96e8", add_sub_cella_6.operation_mode = "arithmetic", add_sub_cella_6.sum_lutc_input = "cin", add_sub_cella_6.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_7 ( .cin(wire_add_sub_cella_6cout[0:0]), .combout(wire_add_sub_cella_combout[7:7]), .dataa(wire_add_sub_cella_dataa[7:7]), .datab(wire_add_sub_cella_datab[7:7])); defparam add_sub_cella_7.cin_used = "true", add_sub_cella_7.lut_mask = "9696", add_sub_cella_7.operation_mode = "normal", add_sub_cella_7.sum_lutc_input = "cin", add_sub_cella_7.lpm_type = "stratix_lcell"; assign wire_add_sub_cella_dataa = dataa, wire_add_sub_cella_datab = datab; assign result = wire_add_sub_cella_combout; endmodule //add32_add_sub_nq7 //VALID FILE module add32 ( dataa, datab, result)/* synthesis synthesis_clearbox = 1 */; input [7:0] dataa; input [7:0] datab; output [7:0] result; wire [7:0] sub_wire0; wire [7:0] result = sub_wire0[7:0]; add32_add_sub_nq7 add32_add_sub_nq7_component ( .dataa (dataa), .datab (datab), .result (sub_wire0)); endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: nBit NUMERIC "8" // Retrieval info: PRIVATE: Function NUMERIC "0" // Retrieval info: PRIVATE: WhichConstant NUMERIC "0" // Retrieval info: PRIVATE: ConstantA NUMERIC "0" // Retrieval info: PRIVATE: ConstantB NUMERIC "0" // Retrieval info: PRIVATE: ValidCtA NUMERIC "0" // Retrieval info: PRIVATE: ValidCtB NUMERIC "0" // Retrieval info: PRIVATE: CarryIn NUMERIC "0" // Retrieval info: PRIVATE: CarryOut NUMERIC "0" // Retrieval info: PRIVATE: Overflow NUMERIC "0" // Retrieval info: PRIVATE: Latency NUMERIC "0" // Retrieval info: PRIVATE: aclr NUMERIC "0" // Retrieval info: PRIVATE: clken NUMERIC "0" // Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD" // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" // Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] // Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0] // Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0] // Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 // Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0 // Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0 // Retrieval info: LIBRARY: lpm lpm.lpm_components.all