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   1 // ////////////////////////////////////////////////////////////////////////////////
   2 // Module Name:    u2_core
   3 // ////////////////////////////////////////////////////////////////////////////////
   4
   5 module u2_core
   6   #(parameter RAM_SIZE=32768)
   7   (// Clocks
   8    input dsp_clk,
   9    input wb_clk,
  10    output clock_ready,
  11    input clk_to_mac,
  12    input pps_in,
  13
  14    // Misc, debug
  15    output [7:0] leds,
  16    output [31:0] debug,
  17    output [1:0] debug_clk,
  18
  19    // Expansion
  20    input exp_pps_in,
  21    output exp_pps_out,
  22
  23    // GMII
  24    //   GMII-CTRL
  25    input GMII_COL,
  26    input GMII_CRS,
  27
  28    //   GMII-TX
  29    output [7:0] GMII_TXD,
  30    output GMII_TX_EN,
  31    output GMII_TX_ER,
  32    output GMII_GTX_CLK,
  33    input GMII_TX_CLK,  // 100mbps clk
  34
  35    //   GMII-RX
  36    input [7:0] GMII_RXD,
  37    input GMII_RX_CLK,
  38    input GMII_RX_DV,
  39    input GMII_RX_ER,
  40
  41    //   GMII-Management
  42    inout MDIO,
  43    output MDC,
  44    input PHY_INTn,   // open drain
  45    output PHY_RESETn,
  46
  47    // SERDES
  48    output ser_enable,
  49    output ser_prbsen,
  50    output ser_loopen,
  51    output ser_rx_en,
  52
  53    output ser_tx_clk,
  54    output [15:0] ser_t,
  55    output ser_tklsb,
  56    output ser_tkmsb,
  57
  58    input ser_rx_clk,
  59    input [15:0] ser_r,
  60    input ser_rklsb,
  61    input ser_rkmsb,
  62
  63    // CPLD interface
  64    output cpld_start,
  65    output cpld_mode,
  66    output cpld_done,
  67    input cpld_din,
  68    input cpld_clk,
  69    input cpld_detached,
  70    output cpld_misc,
  71    input cpld_init_b,
  72    input por,
  73    output config_success,
  74
  75    // ADC
  76    input [13:0] adc_a,
  77    input adc_ovf_a,
  78    output adc_on_a,
  79    output adc_oe_a,
  80
  81    input [13:0] adc_b,
  82    input adc_ovf_b,
  83    output adc_on_b,
  84    output adc_oe_b,
  85
  86    // DAC
  87    output [15:0] dac_a,
  88    output [15:0] dac_b,
  89
  90    // I2C
  91    input scl_pad_i,
  92    output scl_pad_o,
  93    output scl_pad_oen_o,
  94    input sda_pad_i,
  95    output sda_pad_o,
  96    output sda_pad_oen_o,
  97
  98    // Clock Gen Control
  99    output [1:0] clk_en,
 100    output [1:0] clk_sel,
 101    input clk_func,        // FIXME is an input to control the 9510
 102    input clk_status,
 103
 104    // Generic SPI
 105    output sclk,
 106    output mosi,
 107    input miso,
 108    output sen_clk,
 109    output sen_dac,
 110    output sen_tx_db,
 111    output sen_tx_adc,
 112    output sen_tx_dac,
 113    output sen_rx_db,
 114    output sen_rx_adc,
 115    output sen_rx_dac,
 116
 117    // GPIO to DBoards
 118    inout [15:0] io_tx,
 119    inout [15:0] io_rx,
 120
 121    // External RAM
 122    inout [17:0] RAM_D,
 123    output [18:0] RAM_A,
 124    output RAM_CE1n,
 125    output RAM_CENn,
 126    output RAM_CLK,
 127    output RAM_WEn,
 128    output RAM_OEn,
 129    output RAM_LDn,
 130
 131    // Debug stuff
 132    output uart_tx_o,
 133    input uart_rx_i,
 134    output uart_baud_o,
 135    input sim_mode,
 136    input [3:0] clock_divider
 137    );
 138
 139    wire [7:0]   set_addr;
 140    wire [31:0]  set_data;
 141    wire         set_stb;
 142
 143    wire         ram_loader_done;
 144    wire         ram_loader_rst, wb_rst, dsp_rst;
 145
 146    wire [31:0]  status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
 147    wire         bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
 148
 149    wire [31:0]  debug_gpio_0, debug_gpio_1;
 150    wire [31:0]  atr_lines;
 151
 152    wire [31:0]  debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
 153                 debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
 154
 155    wire [15:0]  ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
 156    wire         ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
 157    wire         ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
 158
 159    wire         serdes_link_up;
 160    wire         epoch;
 161
 162    // ///////////////////////////////////////////////////////////////////////////////////////////////
 163    // Wishbone Single Master INTERCON
 164    localparam   dw = 32;  // Data bus width
 165    localparam   aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
 166    localparam   sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.
 167
 168    wire [dw-1:0] m0_dat_o, m0_dat_i;
 169    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
 170                  s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
 171                  s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o,
 172                  s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o;
 173    wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr;
 174    wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel;
 175    wire          m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack;
 176    wire          m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb;
 177    wire          m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc;
 178    wire          m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err;
 179    wire          m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty;
 180    wire          m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we;
 181
 182    wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
 183                 .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
 184                 .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10),
 185                 .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10),
 186                 .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01),
 187                 .dw(dw),.aw(aw),.sw(sw)) wb_1master
 188      (.clk_i(wb_clk),.rst_i(wb_rst),
 189       .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
 190       .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
 191       .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o  (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
 192       .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
 193       .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o  (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
 194       .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
 195       .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o  (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
 196       .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
 197       .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o  (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
 198       .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
 199       .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o  (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
 200       .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
 201       .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o  (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
 202       .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
 203       .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o  (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
 204       .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
 205       .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o  (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
 206       .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty),
 207       .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o  (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
 208       .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty),
 209       .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o  (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
 210       .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
 211       .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb),
 212       .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
 213       .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb),
 214       .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty),
 215       .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb),
 216       .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
 217       .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb),
 218       .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty),
 219       .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb),
 220       .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty),
 221       .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0)  );
 222
 223    //////////////////////////////////////////////////////////////////////////////////////////
 224    // Reset Controller
 225    system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
 226                            .ram_loader_rst_o(ram_loader_rst),
 227                            .wb_rst_o(wb_rst),
 228                            .ram_loader_done_i(ram_loader_done));
 229
 230    assign        config_success = ram_loader_done;
 231    reg           takeover = 0;
 232
 233    wire          cpld_start_int, cpld_mode_int, cpld_done_int;
 234
 235    always @(posedge wb_clk)
 236      if(ram_loader_done)
 237        takeover = 1;
 238    assign        cpld_misc = ~takeover;
 239
 240    wire          sd_clk, sd_csn, sd_mosi, sd_miso;
 241
 242    assign        sd_miso = cpld_din;
 243    assign        cpld_start = takeover ? sd_clk : cpld_start_int;
 244    assign        cpld_mode = takeover ? sd_csn : cpld_mode_int;
 245    assign        cpld_done = takeover ? sd_mosi : cpld_done_int;
 246
 247    // ///////////////////////////////////////////////////////////////////
 248    // RAM Loader
 249
 250    wire [31:0]   ram_loader_dat, iwb_dat;
 251    wire [15:0]   ram_loader_adr, iwb_adr;
 252    wire [3:0]    ram_loader_sel;
 253    wire          ram_loader_stb, ram_loader_we, ram_loader_ack;
 254    wire          iwb_ack, iwb_stb;
 255    ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
 256      ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
 257                  // CPLD Interface
 258                  .cfg_clk_i(cpld_clk),
 259                  .cfg_data_i(cpld_din),
 260                  .start_o(cpld_start_int),
 261                  .mode_o(cpld_mode_int),
 262                  .done_o(cpld_done_int),
 263                  .detached_i(cpld_detached),
 264                  // Wishbone Interface
 265                  .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
 266                  .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
 267                  .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
 268                  .ram_loader_done_o(ram_loader_done));
 269
 270    // Processor
 271    aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
 272      aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
 273            // Instruction Wishbone bus to I-RAM
 274            .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
 275            .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
 276            // Data Wishbone bus to system bus fabric
 277            .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
 278            .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
 279            // Interrupts and exceptions
 280            .sys_int_i(proc_int),.sys_exc_i(bus_error) );
 281
 282    assign        bus_error = m0_err | m0_rty;
 283
 284    // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
 285    // I-port connects directly to processor and ram loader
 286
 287    wire          flush_icache;
 288    ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
 289      sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
 290
 291              .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
 292              .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
 293              .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
 294              .ram_loader_done_i(ram_loader_done),
 295
 296              .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
 297              .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
 298
 299              .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
 300              .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
 301              .flush_icache(flush_icache));
 302
 303    assign        s0_err = 1'b0;
 304    assign        s0_rty = 1'b0;
 305
 306    setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 307                                          .in(set_data),.out(),.changed(flush_icache));
 308
 309    // Buffer Pool, slave #1
 310    wire          rd0_ready_i, rd0_ready_o;
 311    wire          rd1_ready_i, rd1_ready_o;
 312    wire          rd2_ready_i, rd2_ready_o;
 313    wire          rd3_ready_i, rd3_ready_o;
 314    wire [3:0]    rd0_flags, rd1_flags, rd2_flags, rd3_flags;
 315    wire [31:0]   rd0_dat, rd1_dat, rd2_dat, rd3_dat;
 316
 317    wire          wr0_ready_i, wr0_ready_o;
 318    wire          wr1_ready_i, wr1_ready_o;
 319    wire          wr2_ready_i, wr2_ready_o;
 320    wire          wr3_ready_i, wr3_ready_o;
 321    wire [3:0]    wr0_flags, wr1_flags, wr2_flags, wr3_flags;
 322    wire [31:0]   wr0_dat, wr1_dat, wr2_dat, wr3_dat;
 323
 324    buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool
 325      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
 326       .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
 327       .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
 328
 329       .stream_clk(dsp_clk), .stream_rst(dsp_rst),
 330       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
 331       .status(status),.sys_int_o(buffer_int),
 332
 333       .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
 334       .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
 335
 336       // Write Interfaces
 337       .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
 338       .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
 339       .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
 340       .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
 341       // Read Interfaces
 342       .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
 343       .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
 344       .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
 345       .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
 346       );
 347
 348    // SPI -- Slave #2
 349    spi_top shared_spi
 350      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
 351       .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
 352       .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int),
 353       .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
 354       .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
 355
 356    assign        s2_rty = 1'b0;
 357
 358    // I2C -- Slave #3
 359    i2c_master_top #(.ARST_LVL(1))
 360      i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0),
 361           .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
 362           .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
 363           .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
 364           .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
 365           .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
 366
 367    assign        s3_dat_i[31:8] = 24'd0;
 368    assign        s3_err = 1'b0;
 369    assign        s3_rty = 1'b0;
 370
 371    // GPIOs -- Slave #4
 372    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
 373                  .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
 374                  .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
 375                  .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
 376                  .gpio( {io_tx,io_rx} ) );
 377    assign        s4_err = 1'b0;
 378    assign        s4_rty = 1'b0;
 379
 380    // Buffer Pool Status -- Slave #5
 381    wb_readback_mux buff_pool_status
 382      (.wb_clk_i(wb_clk),
 383       .wb_rst_i(wb_rst),
 384       .wb_stb_i(s5_stb),
 385       .wb_adr_i(s5_adr),
 386       .wb_dat_o(s5_dat_i),
 387       .wb_ack_o(s5_ack),
 388
 389       .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
 390       .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
 391       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
 392       .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
 393       );
 394
 395    assign        s5_err  = 1'b0;
 396    assign        s5_rty  = 1'b0;
 397
 398    // /////////////////////////////////////////////////////////////////////////
 399    // Ethernet MAC  Slave #6
 400
 401    simple_gemac_wrapper simple_gemac_wrapper
 402      (.clk125(clk_to_mac),  .reset(wb_rst),
 403       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
 404       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
 405       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
 406       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
 407       .pause_req(0), .pause_time(0),
 408       .sys_clk(dsp_clk),
 409       .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
 410       .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
 411       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
 412       .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
 413       .mdio(MDIO), .mdc(MDC),
 414       .debug(debug_mac));
 415
 416    assign        s6_err  = 1'b0;
 417    assign        s6_rty  = 1'b0;
 418
 419    // /////////////////////////////////////////////////////////////////////////
 420    // Settings Bus -- Slave #7
 421    settings_bus settings_bus
 422      (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
 423       .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
 424       .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
 425
 426    assign        s7_err = 1'b0;
 427    assign        s7_rty = 1'b0;
 428    assign        s7_dat_i = 32'd0;
 429
 430    // Output control lines
 431    wire [7:0]    clock_outs, serdes_outs, adc_outs;
 432    assign        {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
 433    assign        {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
 434    assign        {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
 435
 436    wire          phy_reset;
 437    assign        PHY_RESETn = ~phy_reset;
 438
 439    setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
 440                                       .in(set_data),.out(clock_outs),.changed());
 441    setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 442                                       .in(set_data),.out(serdes_outs),.changed());
 443    setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 444                                       .in(set_data),.out(adc_outs),.changed());
 445    setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 446                                       .in(set_data),.out(phy_reset),.changed());
 447
 448    // /////////////////////////////////////////////////////////////////////////
 449    //  LEDS
 450    //    register 8 determines whether leds are controlled by SW or not
 451    //    1 = controlled by HW, 0 = by SW
 452    //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
 453
 454    wire [7:0]    led_src, led_sw;
 455    wire [7:0]    led_hw = {clk_status,serdes_link_up};
 456
 457    setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 458                                       .in(set_data),.out(led_sw),.changed());
 459    setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 460                                           .in(set_data),.out(led_src),.changed());
 461
 462    assign        leds = (led_src & led_hw) | (~led_src & led_sw);
 463
 464    // /////////////////////////////////////////////////////////////////////////
 465    // Interrupt Controller, Slave #8
 466
 467    wire [15:0]   irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
 468                       {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
 469
 470    simple_pic #(.is(16),.dwidth(32)) simple_pic
 471      (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
 472       .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
 473       .irq(irq) );
 474    assign        s8_err = 0;
 475    assign        s8_rty = 0;
 476
 477    // /////////////////////////////////////////////////////////////////////////
 478    // Master Timer, Slave #9
 479
 480    wire [31:0]   master_time;
 481    timer timer
 482      (.wb_clk_i(wb_clk),.rst_i(wb_rst),
 483       .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
 484       .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
 485       .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
 486    assign        s9_err = 0;
 487    assign        s9_rty = 0;
 488
 489    // /////////////////////////////////////////////////////////////////////////
 490    // UART, Slave #10
 491
 492    simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
 493      (.clk_i(wb_clk),.rst_i(wb_rst),
 494       .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack),
 495       .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i),
 496       .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
 497       .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
 498
 499    assign        s10_err = 0;
 500    assign        s10_rty = 0;
 501
 502    // /////////////////////////////////////////////////////////////////////////
 503    // ATR Controller, Slave #11
 504
 505    wire          run_rx, run_tx;
 506    reg           run_rx_d1;
 507    always @(posedge dsp_clk)
 508      run_rx_d1 <= run_rx;
 509
 510    atr_controller atr_controller
 511      (.clk_i(wb_clk),.rst_i(wb_rst),
 512       .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
 513       .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
 514       .run_rx(run_rx_d1),.run_tx(run_tx),.master_time(), .ctrl_lines(atr_lines) );
 515    assign        s11_err = 0;
 516    assign        s11_rty = 0;
 517
 518    // //////////////////////////////////////////////////////////////////////////
 519    // Time Sync, Slave #12
 520
 521    reg           pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
 522    always @(negedge dsp_clk) pps_negedge <= pps_in;
 523    always @(posedge dsp_clk) pps_posedge <= pps_in;
 524    always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
 525    always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;
 526
 527    wire          pps_o;
 528    time_sync time_sync
 529      (.wb_clk_i(wb_clk),.rst_i(wb_rst),
 530       .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
 531       .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
 532       .sys_clk_i(dsp_clk),.master_time_o(master_time),
 533       .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
 534       .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
 535       .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
 536    assign        s12_err = 0;
 537    assign        s12_rty = 0;
 538
 539    // /////////////////////////////////////////////////////////////////////////
 540    // SD Card Reader / Writer, Slave #13
 541
 542    sd_spi_wb sd_spi_wb
 543      (.clk(wb_clk),.rst(wb_rst),
 544       .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
 545       .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we),
 546       .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i),
 547       .wb_ack_o(s13_ack) );
 548    assign        s13_err = 0;
 549    assign        s13_rty = 0;
 550    // /////////////////////////////////////////////////////////////////////////
 551    // DSP
 552    wire [31:0]   sample_rx, sample_tx;
 553    wire          strobe_rx, strobe_tx;
 554
 555    rx_control #(.FIFOSIZE(10)) rx_control
 556      (.clk(dsp_clk), .rst(dsp_rst),
 557       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
 558       .master_time(master_time),.overrun(overrun),
 559       .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o),
 560       .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
 561       .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
 562       .debug_rx(debug_rx) );
 563
 564    // dummy_rx dsp_core_rx
 565    dsp_core_rx dsp_core_rx
 566      (.clk(dsp_clk),.rst(dsp_rst),
 567       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
 568       .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
 569       .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
 570       .debug(debug_rx_dsp) );
 571
 572    tx_control #(.FIFOSIZE(10)) tx_control
 573      (.clk(dsp_clk), .rst(dsp_rst),
 574       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
 575       .master_time(master_time),.underrun(underrun),
 576       .rd_dat_i(rd1_dat), .rd_flags_i(rd_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i),
 577       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
 578       .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty),
 579       .debug(debug_txc) );
 580
 581    dsp_core_tx dsp_core_tx
 582      (.clk(dsp_clk),.rst(dsp_rst),
 583       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
 584       .dac_a(dac_a),.dac_b(dac_b),
 585       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) );
 586
 587    assign dsp_rst = wb_rst;
 588
 589    // ///////////////////////////////////////////////////////////////////////////////////
 590    // SERDES
 591 /*
 592    serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
 593      (.clk(dsp_clk),.rst(dsp_rst),
 594       .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
 595       .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
 596       .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
 597       .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
 598       .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
 599       .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
 600       .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
 601 */
 602    // ///////////////////////////////////////////////////////////////////////////////////
 603    // External RAM Interface
 604
 605    localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes
 606
 607    wire [15:0] bus2ram, ram2bus;
 608    wire [15:0] bridge_adr;
 609    wire [1:0]  bridge_sel;
 610    wire        bridge_stb, bridge_cyc, bridge_we, bridge_ack;
 611
 612    wire [19:0] page;
 613    wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
 614    setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 615                                        .in(set_data),.out(page),.changed());
 616
 617    wb_bridge_16_32 bridge
 618      (.wb_clk(wb_clk),.wb_rst(wb_rst),
 619       .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel),
 620       .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack),
 621       .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
 622       .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
 623
 624    wb_zbt16_b wb_zbt16_b
 625      (.clk(wb_clk),.rst(wb_rst),
 626       .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
 627       .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
 628       .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
 629       .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
 630       .sram_mode(),.sram_zz() );
 631
 632    assign      s14_err = 0; assign s14_rty = 0;
 633    assign      RAM_CE1n = 0;
 634    assign      RAM_D[17:16] = 2'bzz;
 635
 636    // /////////////////////////////////////////////////////////////////////////////////////////
 637    // Debug Pins
 638
 639    // FIFO Level Debugging
 640    reg [31:0]  host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
 641
 642    always @(posedge dsp_clk)
 643      serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
 644                              {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
 645
 646    always @(posedge dsp_clk)
 647      dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
 648                              {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
 649
 650    always @(posedge dsp_clk)
 651      host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
 652                            {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
 653
 654    always @(posedge dsp_clk)
 655      dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
 656                            {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
 657
 658    always @(posedge dsp_clk)
 659      eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
 660                         {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
 661
 662    assign  debug_clk[0]  = 0; // wb_clk;
 663    assign  debug_clk[1]  = clk_to_mac;
 664 /*
 665
 666    wire        mdio_cpy  = MDIO;
 667    assign  debug         = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] },
 668                              { s6_adr[15:8] },
 669                              { s6_adr[7:0] },
 670                              { 6'd0, mdio_cpy, MDC } };
 671 */
 672 /*
 673    assign debug          = { { GMII_TXD },
 674                              { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK },
 675                              { wr2_flags, rd2_flags },
 676                              { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
 677  */
 678    assign debug          = { { GMII_RXD },
 679                              { 1'd0, debug_mac2[3:0], GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
 680                              { wr2_flags, rd2_flags },
 681                              { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
 682
 683    assign  debug_gpio_0 = debug_mac; //eth_mac_debug;
 684    assign  debug_gpio_1 = 0;
 685
 686 endmodule // u2_core
 687
 688 //   wire        debug_mux;
 689 //   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 690 //                                      .in(set_data),.out(debug_mux),.changed());
 691
 692 //assign     debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
 693 //assign     debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
 694
 695 //assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
 696 //              {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
 697
 698 //assign      debug = debug_tx_dsp;
 699 //assign      debug = debug_serdes0;
 700
 701 //assign      debug_gpio_0 = 0; //debug_serdes0;
 702 //assign      debug_gpio_1 = 0; //debug_serdes1;
 703
 704 //   assign      debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
 705 //            {8'b0},
 706 //      {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
 707 //    {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
 708
 709 //assign      debug = {dac_a,dac_b};
 710
 711 /*
 712  assign      debug = {{ram_loader_done, takeover, 6'd0},
 713  {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi},
 714  {8'd0},
 715  {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */
 716
 717 /*assign      debug = host_to_dsp_fifo;
 718  assign      debug_gpio_0 = eth_mac_debug;
 719  assign      debug_gpio_1 = 0;
 720  */
 721 // Assign various commonly used debug buses.
 722 /*
 723  wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
 724  irq[7:0],
 725  GMII_RXD,
 726  GMII_TXD};
 727
 728  wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
 729
 730    wire [31:0] debug_time =  {uart_tx_o, 7'b0,
 731                               irq[7:0],
 732                               6'b0, GMII_RX_DV, GMII_TX_EN,
 733                               4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
 734
 735    wire [31:0] debug_irq =  {uart_tx_o, iwb_adr, iwb_ack,
 736                              irq[7:0],
 737                              proc_int,  7'b0 };
 738
 739    wire [31:0] debug_eth =
 740                {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
 741                 {8'd0},
 742                 {8'd0},
 743                 {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} };
 744
 745    assign      debug_serdes0 = { { rd0_dat[7:0] },
 746                                  { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done },
 747                                  { ser_t[15:8] },
 748                                  { ser_t[7:0] } };
 749
 750    assign      debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
 751                                  { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
 752                                  { ser_r[15:8] },
 753                                  { ser_r[7:0] } };
 754
 755    assign      debug_gpio_1 = {uart_tx_o,7'd0,
 756                                3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
 757                                debug_txc[15:0]};
 758    assign      debug_gpio_1 = debug_rx;
 759    assign      debug_gpio_1 = debug_serdes1;
 760    assign      debug_gpio_1 = debug_eth;
 761
 762     */
 763