1 ##############################################################
3 # Xilinx Core Generator version K.39
4 # Date: Thu Sep 3 17:25:43 2009
6 ##############################################################
8 # This file contains the customisation parameters for a
9 # Xilinx CORE Generator IP GUI. It is strongly recommended
10 # that you do not manually alter this file as it may cause
11 # unexpected and unsupported behavior.
13 ##############################################################
15 # BEGIN Project Options
18 SET busformat = BusFormatAngleBracketNotRipped
20 SET designentry = VHDL
22 SET devicefamily = spartan3
23 SET flowvendor = Foundation_iSE
24 SET formalverification = False
25 SET foundationsym = False
26 SET implementationfiletype = Ngc
28 SET removerpms = False
29 SET simulationfiles = Behavioral
35 SELECT Fifo_Generator family Xilinx,_Inc. 4.3
38 CSET almost_empty_flag=false
39 CSET almost_full_flag=false
40 CSET component_name=fifo_xlnx_2Kx36_2clk
42 CSET data_count_width=12
43 CSET disable_timing_violations=false
44 CSET dout_reset_value=0
45 CSET empty_threshold_assert_value=4
46 CSET empty_threshold_negate_value=5
48 CSET enable_int_clk=false
49 CSET fifo_implementation=Independent_Clocks_Block_RAM
50 CSET full_flags_reset_value=1
51 CSET full_threshold_assert_value=2047
52 CSET full_threshold_negate_value=2046
53 CSET input_data_width=36
55 CSET output_data_width=36
56 CSET output_depth=2048
57 CSET overflow_flag=false
58 CSET overflow_sense=Active_High
59 CSET performance_options=First_Word_Fall_Through
60 CSET programmable_empty_type=No_Programmable_Empty_Threshold
61 CSET programmable_full_type=No_Programmable_Full_Threshold
62 CSET read_clock_frequency=1
63 CSET read_data_count=true
64 CSET read_data_count_width=12
66 CSET reset_type=Asynchronous_Reset
67 CSET underflow_flag=false
68 CSET underflow_sense=Active_High
69 CSET use_dout_reset=true
70 CSET use_embedded_registers=false
71 CSET use_extra_logic=true
73 CSET valid_sense=Active_High
74 CSET write_acknowledge_flag=false
75 CSET write_acknowledge_sense=Active_High
76 CSET write_clock_frequency=1
77 CSET write_data_count=true
78 CSET write_data_count_width=12