6 (input clk_in, input [WIDTH-1:0] addr_in,
7 input clk_out, output reg [WIDTH-1:0] addr_out);
9 reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1;
10 wire [WIDTH-1:0] gray, bin;
12 bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) );
14 always @(posedge clk_in)
17 always @(posedge clk_out)
18 gray_clkout <= gray_clkin;
20 always @(posedge clk_out)
21 gray_clkout_d1 <= gray_clkout;
23 gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) );
25 // FIXME we may not need the next register, but it may help timing
26 always @(posedge clk_out)
29 endmodule // gray_send