2 * Copyright 2007,2008 Free Software Foundation, Inc.
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "memory_map.h"
26 #include "buffer_pool.h"
31 #include "usrp2_eth_packet.h"
33 #include "app_common_v2.h"
34 #include "memcpy_wa.h"
41 #define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
44 static int fw_seqno; // used when f/w is filling in sequence numbers
49 * Full duplex Tx and Rx between serdes and DSP pipelines
51 * Buffer 1 is used by the cpu to send frames to the host.
52 * Buffers 2 and 3 are used to double-buffer the DSP Rx to serdes flow
53 * Buffers 4 and 5 are used to double-buffer the serdes to DSP Tx flow
55 //#define CPU_RX_BUF 0 // eth -> cpu
57 #define DSP_RX_BUF_0 2 // dsp rx -> serdes (double buffer)
58 #define DSP_RX_BUF_1 3 // dsp rx -> serdes
59 #define DSP_TX_BUF_0 4 // serdes -> dsp tx (double buffer)
60 #define DSP_TX_BUF_1 5 // serdes -> dsp tx
63 * ==================================================================
64 * configure DSP TX double buffering state machine (serdes -> dsp)
65 * ==================================================================
68 // 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
69 // DSP Tx reads word0 (flags) + timestamp followed by samples
71 #define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
73 // Receive from serdes
74 buf_cmd_args_t dsp_tx_recv_args = {
81 buf_cmd_args_t dsp_tx_send_args = {
83 DSP_TX_FIRST_LINE, // starts just past transport header
84 0 // filled in from last_line register
87 dbsm_t dsp_tx_sm; // the state machine
90 * =================================================================
91 * configure DSP RX double buffering state machine (dsp -> serdes)
92 * =================================================================
95 // 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
96 // DSP Rx writes timestamp followed by nlines_per_frame of samples
97 #define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
100 buf_cmd_args_t dsp_rx_recv_args = {
107 buf_cmd_args_t dsp_rx_send_args = {
109 0, // starts with ethernet header in line 0
110 0, // filled in from list_line register
113 dbsm_t dsp_rx_sm; // the state machine
116 // The mac address of the host we're sending to.
117 u2_mac_addr_t host_mac_addr;
120 // variables for streaming mode
122 static bool streaming_p = false;
123 static unsigned int streaming_items_per_frame = 0;
124 static int streaming_frame_count = 0;
125 #define FRAMES_PER_CMD 1000
128 // ----------------------------------------------------------------
132 restart_streaming(void)
135 dsp_rx_regs->clear_state = 1; // reset
138 streaming_frame_count = FRAMES_PER_CMD;
140 dsp_rx_regs->rx_command =
141 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
142 streaming_items_per_frame,
143 1, 1); // set "chain" bit
145 // kick off the state machine
146 dbsm_start(&dsp_rx_sm);
148 dsp_rx_regs->rx_time = 0; // enqueue first of two commands
150 // make sure this one and the rest have the "now" and "chain" bits set.
151 dsp_rx_regs->rx_command =
152 MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
153 streaming_items_per_frame,
156 dsp_rx_regs->rx_time = 0; // enqueue second command
160 start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
162 host_mac_addr = *host; // remember who we're sending to
165 * Construct ethernet header and word0 and preload into two buffers
168 memset(&pkt, 0, sizeof(pkt));
169 pkt.ehdr.dst = *host;
170 pkt.ehdr.ethertype = U2_ETHERTYPE;
171 u2p_set_word0(&pkt.fixed, 0, 0);
172 // DSP RX will fill in timestamp
174 memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
175 memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
181 streaming_items_per_frame = p->items_per_frame;
190 dsp_rx_regs->clear_state = 1; // flush cmd queue
191 bp_clear_buf(DSP_RX_BUF_0);
192 bp_clear_buf(DSP_RX_BUF_1);
199 dsp_tx_regs->clear_state = 1;
200 bp_clear_buf(DSP_TX_BUF_0);
201 bp_clear_buf(DSP_TX_BUF_1);
206 // setup some defaults
208 dsp_tx_regs->freq = 0;
209 dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
210 dsp_tx_regs->interp_rate = interp;
216 * Debugging ONLY. This will be handled by the tx_protocol_engine.
218 * This is called when the DSP Rx chain has filled in a packet.
219 * We set and increment the seqno, then return false, indicating
220 * that we didn't handle the packet. A bit of a kludge
221 * but it should work.
224 fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
226 uint32_t *p = buffer_ram(buf_this);
227 uint32_t seqno = fw_seqno++;
229 // KLUDGE all kinds of nasty magic numbers and embedded knowledge
231 t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
234 // queue up another rx command when required
235 if (streaming_p && --streaming_frame_count == 0){
236 streaming_frame_count = FRAMES_PER_CMD;
237 dsp_rx_regs->rx_time = 0;
240 return false; // we didn't handle the packet
246 buffer_irq_handler(unsigned irq)
248 uint32_t status = buffer_pool_status->status;
250 dbsm_process_status(&dsp_tx_sm, status);
251 dbsm_process_status(&dsp_rx_sm, status);
259 putstr("\nSERDES TxRx\n");
261 cpu_tx_buf_dest_port = PORT_SERDES;
263 ethernet_register_link_changed_callback(link_changed_callback);
266 clocks_mimo_config(MC_WE_LOCK_TO_MIMO);
269 // make bit 15 of Tx gpio's be a s/w output
270 hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
271 hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
275 output_regs->debug_mux_ctrl = 1;
276 hal_gpio_set_sels(GPIO_TX_BANK, "0000000000000000");
277 hal_gpio_set_sels(GPIO_RX_BANK, "0000000000000000");
278 hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
279 hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
283 // initialize double buffering state machine for ethernet -> DSP Tx
285 dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
286 &dsp_tx_recv_args, &dsp_tx_send_args,
290 // initialize double buffering state machine for DSP RX -> Ethernet
293 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
294 &dsp_rx_recv_args, &dsp_rx_send_args,
295 fw_sets_seqno_inspector);
298 dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
299 &dsp_rx_recv_args, &dsp_rx_send_args,
303 // tell app_common that this dbsm could be sending to the ethernet
304 ac_could_be_sending_to_eth = &dsp_rx_sm;
307 // program tx registers
310 // kick off the state machine
311 dbsm_start(&dsp_tx_sm);
316 // hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
319 buffer_irq_handler(0);
321 int pending = pic_regs->pending; // poll for under or overrun
323 if (pending & PIC_UNDERRUN_INT){
324 dbsm_handle_tx_underrun(&dsp_tx_sm);
325 pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
329 if (pending & PIC_OVERRUN_INT){
330 dbsm_handle_rx_overrun(&dsp_rx_sm);
331 pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
333 // FIXME Figure out how to handle this robustly.
334 // Any buffers that are emptying should be allowed to drain...
337 // restart_streaming();
338 // FIXME report error
341 // FIXME report error