3 * Copyright 2007,2008 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "app_common_v2.h"
24 #include "buffer_pool.h"
25 #include "memcpy_wa.h"
28 #include "print_rmon_regs.h"
34 volatile bool link_is_up = false; // eth handler sets this
35 int cpu_tx_buf_dest_port = PORT_ETH;
37 // If this is non-zero, this dbsm could be writing to the ethernet
38 dbsm_t *ac_could_be_sending_to_eth;
40 static unsigned char exp_seqno __attribute__((unused)) = 0;
44 burn_mac_addr(const op_burn_mac_addr_t *p)
46 return ethernet_set_mac_addr(&p->addr);
50 config_mimo_cmd(const op_config_mimo_t *p)
52 clocks_mimo_config(p->flags);
57 set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt)
59 reply_pkt->ehdr.dst = cmd_pkt->ehdr.src;
60 reply_pkt->ehdr.ethertype = U2_ETHERTYPE;
61 reply_pkt->thdr.flags = 0;
62 reply_pkt->thdr.fifo_status = 0; // written by protocol engine
63 reply_pkt->thdr.seqno = 0; // written by protocol engine
64 reply_pkt->thdr.ack = 0; // written by protocol engine
65 u2p_set_word0(&reply_pkt->fixed, 0, CONTROL_CHAN);
66 reply_pkt->fixed.timestamp = timer_regs->time;
70 send_reply(unsigned char *reply, size_t reply_len)
75 // wait for buffer to become idle
76 hal_set_leds(0x4, 0x4);
77 while((buffer_pool_status->status & BPS_IDLE(CPU_TX_BUF)) == 0)
79 hal_set_leds(0x0, 0x4);
81 // copy reply into CPU_TX_BUF
82 memcpy_wa(buffer_ram(CPU_TX_BUF), reply, reply_len);
84 // wait until nobody else is sending to the ethernet
85 if (ac_could_be_sending_to_eth){
86 hal_set_leds(0x8, 0x8);
87 dbsm_wait_for_opening(ac_could_be_sending_to_eth);
88 hal_set_leds(0x0, 0x8);
92 printf("sending_reply to port %d, len = %d\n", cpu_tx_buf_dest_port, reply_len);
93 print_buffer(buffer_ram(CPU_TX_BUF), reply_len/4);
97 bp_send_from_buf(CPU_TX_BUF, cpu_tx_buf_dest_port, 1, 0, reply_len/4);
99 // wait for it to complete (not long, it's a small pkt)
100 while((buffer_pool_status->status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))) == 0)
103 bp_clear_buf(CPU_TX_BUF);
108 op_id_cmd(const op_generic_t *p,
109 void *reply_payload, size_t reply_payload_space)
111 op_id_reply_t *r = (op_id_reply_t *) reply_payload;
112 if (reply_payload_space < sizeof(*r)) // no room
115 // Build reply subpacket
117 r->opcode = OP_ID_REPLY;
118 r->len = sizeof(op_id_reply_t);
120 r->addr = *ethernet_mac_addr();
121 r->hw_rev = (u2_hw_rev_major << 8) | u2_hw_rev_minor;
122 // r->fpga_md5sum = ; // FIXME
123 // r->sw_md5sum = ; // FIXME
125 // FIXME Add d'board info, including dbid, min/max gain, min/max freq
132 config_tx_v2_cmd(const op_config_tx_v2_t *p,
133 void *reply_payload, size_t reply_payload_space)
135 op_config_tx_reply_v2_t *r = (op_config_tx_reply_v2_t *) reply_payload;
136 if (reply_payload_space < sizeof(*r))
139 struct tune_result tune_result;
140 memset(&tune_result, 0, sizeof(tune_result));
144 if (p->valid & CFGV_GAIN){
145 ok &= db_set_gain(tx_dboard, p->gain);
148 if (p->valid & CFGV_FREQ){
149 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
150 bool tune_ok = db_tune(tx_dboard, f, &tune_result);
152 print_tune_result("Tx", tune_ok, f, &tune_result);
155 if (p->valid & CFGV_INTERP_DECIM){
156 int interp = p->interp;
162 interp = interp >> 1;
167 interp = interp >> 1;
170 if (p->interp < MIN_INTERP || p->interp > MAX_INTERP)
173 dsp_tx_regs->interp_rate = (hb1<<9) | (hb2<<8) | interp;
174 // printf("Interp: %d, register %d\n", p->interp, (hb1<<9) | (hb2<<8) | interp);
178 if (p->valid & CFGV_SCALE_IQ){
179 dsp_tx_regs->scale_iq = p->scale_iq;
182 // Build reply subpacket
184 r->opcode = OP_CONFIG_TX_REPLY_V2;
188 r->inverted = tune_result.inverted;
189 r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
190 r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
191 r->duc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
192 r->duc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
193 r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
194 r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
199 config_rx_v2_cmd(const op_config_rx_v2_t *p,
200 void *reply_payload, size_t reply_payload_space)
202 op_config_rx_reply_v2_t *r = (op_config_rx_reply_v2_t *) reply_payload;
203 if (reply_payload_space < sizeof(*r))
206 struct tune_result tune_result;
207 memset(&tune_result, 0, sizeof(tune_result));
211 if (p->valid & CFGV_GAIN){
212 ok &= db_set_gain(rx_dboard, p->gain);
215 if (p->valid & CFGV_FREQ){
216 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
217 bool tune_ok = db_tune(rx_dboard, f, &tune_result);
219 print_tune_result("Rx", tune_ok, f, &tune_result);
222 if (p->valid & CFGV_INTERP_DECIM){
223 int decim = p->decim;
237 if (decim < MIN_DECIM || decim > MAX_DECIM)
240 dsp_rx_regs->decim_rate = (hb1<<9) | (hb2<<8) | decim;
241 // printf("Decim: %d, register %d\n", p->decim, (hb1<<9) | (hb2<<8) | decim);
245 if (p->valid & CFGV_SCALE_IQ){
246 dsp_rx_regs->scale_iq = p->scale_iq;
249 // Build reply subpacket
251 r->opcode = OP_CONFIG_RX_REPLY_V2;
255 r->inverted = tune_result.inverted;
256 r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
257 r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
258 r->ddc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
259 r->ddc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
260 r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
261 r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
267 read_time_cmd(const op_generic_t *p,
268 void *reply_payload, size_t reply_payload_space)
270 op_read_time_reply_t *r = (op_read_time_reply_t *) reply_payload;
271 if (reply_payload_space < sizeof(*r))
274 r->opcode = OP_READ_TIME_REPLY;
277 r->time = timer_regs->time;
283 generic_reply(const op_generic_t *p,
284 void *reply_payload, size_t reply_payload_space,
287 op_generic_t *r = (op_generic_t *) reply_payload;
288 if (reply_payload_space < sizeof(*r))
291 r->opcode = p->opcode | OP_REPLY_BIT;
300 add_eop(void *reply_payload, size_t reply_payload_space)
302 op_generic_t *r = (op_generic_t *) reply_payload;
303 if (reply_payload_space < sizeof(*r))
315 handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len)
317 unsigned char reply[sizeof(u2_eth_packet_t) + 4 * sizeof(u2_subpkt_t)] _AL4;
318 unsigned char *reply_payload = &reply[sizeof(u2_eth_packet_t)];
319 int reply_payload_space = sizeof(reply) - sizeof(u2_eth_packet_t);
322 memset(reply, 0, sizeof(reply));
323 set_reply_hdr((u2_eth_packet_t *) reply, pkt);
325 // point to beginning of payload (subpackets)
326 unsigned char *payload = ((unsigned char *) pkt) + sizeof(u2_eth_packet_t);
327 int payload_len = len - sizeof(u2_eth_packet_t);
329 size_t subpktlen = 0;
331 while (payload_len >= sizeof(op_generic_t)){
332 const op_generic_t *gp = (const op_generic_t *) payload;
336 case OP_EOP: // end of subpackets
337 goto end_of_subpackets;
340 subpktlen = op_id_cmd(gp, reply_payload, reply_payload_space);
343 case OP_CONFIG_TX_V2:
344 subpktlen = config_tx_v2_cmd((op_config_tx_v2_t *) payload,
345 reply_payload, reply_payload_space);
348 case OP_CONFIG_RX_V2:
349 subpktlen = config_rx_v2_cmd((op_config_rx_v2_t *) payload,
350 reply_payload, reply_payload_space);
353 case OP_START_RX_STREAMING:
354 start_rx_streaming_cmd(&pkt->ehdr.src, (op_start_rx_streaming_t *) payload);
355 subpktlen = generic_reply(gp, reply_payload, reply_payload_space, true);
360 subpktlen = generic_reply(gp, reply_payload, reply_payload_space, true);
363 case OP_BURN_MAC_ADDR:
364 subpktlen = generic_reply(gp, reply_payload, reply_payload_space,
365 burn_mac_addr((op_burn_mac_addr_t *) payload));
369 subpktlen = generic_reply(gp, reply_payload, reply_payload_space,
370 config_mimo_cmd((op_config_mimo_t *) payload));
374 subpktlen = read_time_cmd(gp, reply_payload, reply_payload_space);
378 printf("app_common_v2: unhandled opcode = %d\n", gp->opcode);
382 int t = (gp->len + 3) & ~3; // bump to a multiple of 4
386 subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
387 reply_payload += subpktlen;
388 reply_payload_space -= subpktlen;
393 // add the EOP marker
394 subpktlen = add_eop(reply_payload, reply_payload_space);
395 subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
396 reply_payload += subpktlen;
397 reply_payload_space -= subpktlen;
399 send_reply(reply, reply_payload - reply);
404 * Called when an ethernet packet is received.
405 * Return true if we handled it here, otherwise
406 * it'll be passed on to the DSP Tx pipe
409 eth_pkt_inspector(dbsm_t *sm, int bufno)
411 u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno);
412 size_t byte_len = (buffer_pool_status->last_line[bufno] - 3) * 4;
414 //static size_t last_len = 0;
416 // hal_toggle_leds(0x1);
418 // inspect rcvd frame and figure out what do do.
420 if (pkt->ehdr.ethertype != U2_ETHERTYPE)
421 return true; // ignore, probably bogus PAUSE frame from MAC
423 int chan = u2p_chan(&pkt->fixed);
427 handle_control_chan_frame(pkt, byte_len);
428 return true; // we handled the packet
435 if (byte_len != last_len){
436 printf("Len: %d last: %d\n", byte_len, last_len);
441 if((pkt->thdr.seqno) == exp_seqno){
447 //printf("S%d %d ",exp_seqno,pkt->thdr.seqno);
448 exp_seqno = pkt->thdr.seqno + 1;
451 return false; // pass it on to Tx DSP
457 * Called when eth phy state changes (w/ interrupts disabled)
460 link_changed_callback(int speed)
462 link_is_up = speed != 0;
463 hal_set_leds(link_is_up ? 0x20 : 0x0, 0x20);
464 printf("\neth link changed: speed = %d\n", speed);
469 print_tune_result(char *msg, bool tune_ok,
470 u2_fxpt_freq_t target_freq, struct tune_result *r)
472 printf("db_tune %s %s\n", msg, tune_ok ? "true" : "false");
473 putstr(" target_freq "); print_fxpt_freq(target_freq); newline();
474 putstr(" baseband_freq "); print_fxpt_freq(r->baseband_freq); newline();
475 putstr(" dxc_freq "); print_fxpt_freq(r->dxc_freq); newline();
476 putstr(" residual_freq "); print_fxpt_freq(r->residual_freq); newline();
477 printf(" inverted %s\n", r->inverted ? "true" : "false");