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   1 //
   2 // Copyright 2009 Free Software Foundation, Inc.
   3 //
   4 // This file is part of GNU Radio
   5 //
   6 // GNU Radio is free software; you can redistribute it and/or modify
   7 // it under the terms of the GNU General Public License as published by
   8 // the Free Software Foundation; either asversion 3, or (at your option)
   9 // any later version.
  10 //
  11 // GNU Radio is distributed in the hope that it will be useful,
  12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 // GNU General Public License for more details.
  15 //
  16 // You should have received a copy of the GNU General Public License
  17 // along with GNU Radio; see the file COPYING.  If not, write to
  18 // the Free Software Foundation, Inc., 51 Franklin Street,
  19 // Boston, MA 02110-1301, USA.
  20
  21 #include "db_wbxng_adf4350_regs.h"
  22 #include "db_wbxng_adf4350.h"
  23
  24 //#include "cal_div.h"
  25
  26 /* reg 0 */
  27 /* reg 1 */
  28 const uint16_t adf4350_regs::s_phase = 0;
  29 /* reg 2 */
  30 const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 3;
  31 const uint8_t adf4350_regs::s_muxout = 6;
  32 const uint8_t adf4350_regs::s_reference_doubler = 0;
  33 const uint8_t adf4350_regs::s_rdiv2 = 0;
  34 const uint8_t adf4350_regs::s_double_buff = 0;
  35 const uint8_t adf4350_regs::s_charge_pump_setting = 5;
  36 const uint8_t adf4350_regs::s_ldf = 0;
  37 const uint8_t adf4350_regs::s_ldp = 0;
  38 const uint8_t adf4350_regs::s_pd_polarity = 1;
  39 const uint8_t adf4350_regs::s_power_down = 0;
  40 const uint8_t adf4350_regs::s_cp_three_state = 0;
  41 const uint8_t adf4350_regs::s_counter_reset = 0;
  42 /* reg 3 */
  43 const uint8_t adf4350_regs::s_csr = 0;
  44 const uint8_t adf4350_regs::s_clk_div_mode = 0;
  45 const uint16_t adf4350_regs::s_12_bit_clock_divider_value = 0;
  46 /* reg 4 */
  47 const uint8_t adf4350_regs::s_feedback_select = 1;
  48 const uint8_t adf4350_regs::s_vco_power_down = 0;
  49 const uint8_t adf4350_regs::s_mtld = 0;
  50 const uint8_t adf4350_regs::s_aux_output_select = 1;
  51 const uint8_t adf4350_regs::s_aux_output_enable = 0;
  52 const uint8_t adf4350_regs::s_aux_output_power = 0;
  53 const uint8_t adf4350_regs::s_rf_output_enable = 1;
  54 const uint8_t adf4350_regs::s_output_power = 3;
  55 /* reg 5 */
  56 const uint8_t adf4350_regs::s_ld_pin_mode = 1;
  57
  58 adf4350_regs::adf4350_regs(adf4350* _adf4350){
  59     d_adf4350 = _adf4350;
  60
  61     /* reg 0 */
  62     d_int = uint16_t(100);
  63     d_frac = 0;
  64     /* reg 1 */
  65     d_prescaler = uint8_t(0);
  66     d_mod = uint16_t(0xfff);                      /* max fractional accuracy */
  67     /* reg 2 */
  68     d_10_bit_r_counter = uint16_t(2);
  69     /* reg 3 */
  70     /* reg 4 */
  71     d_divider_select = 0;
  72     d_8_bit_band_select_clock_divider_value = 0;
  73     /* reg 5 */
  74 }
  75
  76 adf4350_regs::~adf4350_regs(void){
  77 }
  78
  79 uint32_t
  80 adf4350_regs::_reg_shift(uint32_t data, uint32_t shift){
  81         return data << shift;
  82     }
  83
  84 void
  85 adf4350_regs::_load_register(uint8_t addr){
  86         uint32_t data;
  87         switch (addr){
  88                 case 0: data = (
  89                         _reg_shift(d_int, 15)                           |
  90                         _reg_shift(d_frac, 3)); break;
  91                 case 1: data = (
  92                         _reg_shift(d_prescaler, 27)                     |
  93                         _reg_shift(s_phase, 15)                         |
  94                         _reg_shift(d_mod, 3)); break;
  95                 case 2: data = (
  96                         _reg_shift(s_low_noise_and_low_spur_modes, 29)  |
  97                         _reg_shift(s_muxout, 26)                        |
  98                         _reg_shift(s_reference_doubler, 25)             |
  99                         _reg_shift(s_rdiv2, 24)                         |
 100                         _reg_shift(d_10_bit_r_counter, 14)              |
 101                         _reg_shift(s_double_buff, 13)                   |
 102                         _reg_shift(s_charge_pump_setting, 9)            |
 103                         _reg_shift(s_ldf, 8)                            |
 104                         _reg_shift(s_ldp, 7)                            |
 105                         _reg_shift(s_pd_polarity, 6)                    |
 106                         _reg_shift(s_power_down, 5)                     |
 107                         _reg_shift(s_cp_three_state, 4)                 |
 108                         _reg_shift(s_counter_reset, 3)); break;
 109                 case 3: data = (
 110                         _reg_shift(s_csr, 18)                           |
 111                         _reg_shift(s_clk_div_mode, 15)                  |
 112                         _reg_shift(s_12_bit_clock_divider_value, 3)); break;
 113                 case 4: data = (
 114                         _reg_shift(s_feedback_select, 23)               |
 115                         _reg_shift(d_divider_select, 20)                |
 116                         _reg_shift(d_8_bit_band_select_clock_divider_value, 12) |
 117                         _reg_shift(s_vco_power_down, 11)                |
 118                         _reg_shift(s_mtld, 10)                          |
 119                         _reg_shift(s_aux_output_select, 9)              |
 120                         _reg_shift(s_aux_output_enable, 8)              |
 121                         _reg_shift(s_aux_output_power, 6)               |
 122                         _reg_shift(s_rf_output_enable, 5)               |
 123                         _reg_shift(s_output_power, 3)); break;
 124                 case 5: data = (
 125                         _reg_shift(s_ld_pin_mode, 22)); break;
 126                 default: return;
 127         }
 128         /* write the data out to spi */
 129         d_adf4350->_write(addr, data);
 130 }