3 module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);
5 always @(posedge clock)
7 3'd0 : data <= #1 -16'd16;
8 3'd1 : data <= #1 16'd74;
9 3'd2 : data <= #1 -16'd254;
10 3'd3 : data <= #1 16'd669;
11 3'd4 : data <= #1 -16'd1468;
12 3'd5 : data <= #1 16'd2950;
13 3'd6 : data <= #1 -16'd6158;
14 3'd7 : data <= #1 16'd20585;
17 endmodule // coeff_rom