1 module chan_fifo_reader
2 (reset, tx_clock, tx_strobe, timestamp_clock, samples_format,
3 fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
4 underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
8 input wire tx_strobe ; //signal to output tx_i and tx_q
9 input wire [31:0] timestamp_clock ; //current time
10 input wire [3:0] samples_format ;// not useful at this point
11 input wire [31:0] fifodata ; //the data input
12 input wire pkt_waiting ; //signal the next packet is ready
13 output reg rdreq ; //actually an ack to the current fifodata
14 output reg skip ; //finish reading current packet
15 output reg [15:0] tx_q ; //top 16 bit output of fifodata
16 output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
18 output reg tx_empty ; //cause 0 to be the output
19 input wire [31:0] rssi;
20 input wire [31:0] threshhold;
21 input wire [31:0] rssi_wait;
23 output wire [14:0] debug;
24 assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
27 // 16 bits interleaved complex samples
31 parameter IDLE = 3'd0;
32 parameter HEADER = 3'd1;
33 parameter TIMESTAMP = 3'd2;
34 parameter WAIT = 3'd3;
35 parameter WAITSTROBE = 3'd4;
36 parameter SEND = 3'd5;
41 `define STARTOFBURST 28
46 reg [2:0] reader_state;
48 reg [6:0] payload_len;
56 always @(posedge tx_clock)
78 * reset all the variables and wait for a tx_strobe
79 * it is assumed that the ram connected to this fifo_reader
80 * is a short hand fifo meaning that the header to the next packet
81 * is already available to this fifo_reader when pkt_waiting is on
87 reader_state <= HEADER;
91 if (burst == 1 && pkt_waiting == 0)
103 rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
104 //Check Start/End burst flag
105 if (fifodata[`STARTOFBURST] == 1
106 && fifodata[`ENDOFBURST] == 1)
108 else if (fifodata[`STARTOFBURST] == 1)
110 else if (fifodata[`ENDOFBURST] == 1)
113 if (trash == 1 && fifodata[`STARTOFBURST] == 0)
116 reader_state <= IDLE;
121 payload_len <= fifodata[`PAYLOAD] ;
124 reader_state <= TIMESTAMP;
130 timestamp <= fifodata;
131 reader_state <= WAIT;
137 // Decide if we wait, send or discard samples
143 time_wait <= time_wait + 32'd1;
145 if ((timestamp < timestamp_clock) ||
146 (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
149 reader_state <= IDLE;
153 else if (timestamp == timestamp_clock
154 || timestamp == 32'hFFFFFFFF)
156 if (rssi <= threshhold || rssi_flag == 0)
159 reader_state <= WAITSTROBE;
162 reader_state <= WAIT;
165 reader_state <= WAIT;
168 // Wait for the transmit chain to be ready
171 // If end of payload...
172 if (read_len == payload_len)
174 reader_state <= IDLE;
179 else if (tx_strobe == 1)
181 reader_state <= SEND;
186 // Send the samples to the tx_chain
189 reader_state <= WAITSTROBE;
190 read_len <= read_len + 7'd1;
197 tx_i <= fifodata[15:0];
198 tx_q <= fifodata[31:16];
201 // Assume 16 bits complex samples by default
204 tx_i <= fifodata[15:0];
205 tx_q <= fifodata[31:16];
213 reader_state <= IDLE;