1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2015 by David Ung *
5 ***************************************************************************/
7 #ifndef OPENOCD_TARGET_ARMV8_H
8 #define OPENOCD_TARGET_ARMV8_H
10 #include "arm_adi_v5.h"
12 #include "armv4_5_mmu.h"
13 #include "armv4_5_cache.h"
14 #include "armv8_dpm.h"
104 enum run_control_op {
105 ARMV8_RUNCONTROL_UNKNOWN = 0,
106 ARMV8_RUNCONTROL_RESUME = 1,
107 ARMV8_RUNCONTROL_HALT = 2,
108 ARMV8_RUNCONTROL_STEP = 3,
111 #define ARMV8_COMMON_MAGIC 0x0A450AAAU
113 /* VA to PA translation operations opc2 values*/
122 /* L210/L220 cache controller support */
123 struct armv8_l2x_cache {
128 struct armv8_cachesize {
130 /* cache dimensioning */
132 uint32_t associativity;
135 /* info for set way operation on cache */
137 uint32_t index_shift;
142 /* information about one architecture cache at any level */
143 struct armv8_arch_cache {
144 int ctype; /* cache type, CLIDR encoding */
145 struct armv8_cachesize d_u_size; /* data cache */
146 struct armv8_cachesize i_size; /* instruction cache */
149 struct armv8_cache_common {
154 struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
156 int d_u_cache_enabled;
158 /* l2 external unified cache if some */
160 int (*flush_all_data_cache)(struct target *target);
161 int (*display_cache_info)(struct command_invocation *cmd,
162 struct armv8_cache_common *armv8_cache);
165 struct armv8_mmu_common {
166 /* following field mmu working way */
167 int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
168 uint64_t ttbr0_mask;/* masked to be used */
170 uint32_t ttbcr; /* cache for ttbcr register */
171 uint32_t ttbr_mask[2];
172 uint32_t ttbr_range[2];
174 int (*read_physical_memory)(struct target *target, target_addr_t address,
175 uint32_t size, uint32_t count, uint8_t *buffer);
176 struct armv8_cache_common armv8_cache;
177 uint32_t mmu_enabled;
180 struct armv8_common {
181 unsigned int common_magic;
184 struct reg_cache *core_cache;
186 /* Core Debug Unit */
188 target_addr_t debug_base;
189 struct adiv5_ap *debug_ap;
191 const uint32_t *opcodes;
194 uint8_t multi_processor_system;
198 /* armv8 aarch64 need below information for page translation */
204 struct armv8_mmu_common armv8_mmu;
208 /* last run-control command issued to this target (resume, halt, step) */
209 enum run_control_op last_run_control_op;
211 /* Direct processor core register read and writes */
212 int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
213 int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
215 /* SIMD/FPU registers read/write interface */
216 int (*read_reg_u128)(struct armv8_common *armv8, int num,
217 uint64_t *lvalue, uint64_t *hvalue);
218 int (*write_reg_u128)(struct armv8_common *armv8, int num,
219 uint64_t lvalue, uint64_t hvalue);
221 int (*examine_debug_reason)(struct target *target);
222 int (*post_debug_entry)(struct target *target);
224 void (*pre_restore_context)(struct target *target);
227 static inline struct armv8_common *
228 target_to_armv8(struct target *target)
230 return container_of(target->arch_info, struct armv8_common, arm);
233 static inline bool is_armv8(struct armv8_common *armv8)
235 return armv8->common_magic == ARMV8_COMMON_MAGIC;
238 /* register offsets from armv8.debug_base */
239 #define CPUV8_DBG_MAINID0 0xD00
240 #define CPUV8_DBG_CPUFEATURE0 0xD20
241 #define CPUV8_DBG_DBGFEATURE0 0xD28
242 #define CPUV8_DBG_MEMFEATURE0 0xD38
244 #define CPUV8_DBG_LOCKACCESS 0xFB0
245 #define CPUV8_DBG_LOCKSTATUS 0xFB4
247 #define CPUV8_DBG_EDESR 0x20
248 #define CPUV8_DBG_EDECR 0x24
249 #define CPUV8_DBG_EDWAR0 0x30
250 #define CPUV8_DBG_EDWAR1 0x34
251 #define CPUV8_DBG_DSCR 0x088
252 #define CPUV8_DBG_DRCR 0x090
253 #define CPUV8_DBG_ECCR 0x098
254 #define CPUV8_DBG_PRCR 0x310
255 #define CPUV8_DBG_PRSR 0x314
257 #define CPUV8_DBG_DTRRX 0x080
258 #define CPUV8_DBG_ITR 0x084
259 #define CPUV8_DBG_SCR 0x088
260 #define CPUV8_DBG_DTRTX 0x08c
262 #define CPUV8_DBG_BVR_BASE 0x400
263 #define CPUV8_DBG_BCR_BASE 0x408
264 #define CPUV8_DBG_WVR_BASE 0x800
265 #define CPUV8_DBG_WCR_BASE 0x808
266 #define CPUV8_DBG_VCR 0x01C
268 #define CPUV8_DBG_OSLAR 0x300
270 #define CPUV8_DBG_AUTHSTATUS 0xFB8
272 #define PAGE_SIZE_4KB 0x1000
273 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
274 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
275 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
276 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
278 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
279 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
280 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
281 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
283 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
285 int armv8_arch_state(struct target *target);
286 int armv8_read_mpidr(struct armv8_common *armv8);
287 int armv8_identify_cache(struct armv8_common *armv8);
288 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
289 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
290 target_addr_t *val, int meminfo);
291 int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
293 int armv8_handle_cache_info_command(struct command_invocation *cmd,
294 struct armv8_cache_common *armv8_cache);
296 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
298 static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
305 case ARM_MODE_ABT: /* FIXME: EL3? */
306 case ARM_MODE_IRQ: /* FIXME: EL3? */
307 case ARM_MODE_FIQ: /* FIXME: EL3? */
308 case ARM_MODE_UND: /* FIXME: EL3? */
309 case ARM_MODE_SYS: /* FIXME: EL3? */
311 /* case ARM_MODE_HYP:
316 /* all Aarch64 modes */
318 return (core_mode >> 2) & 3;
322 const char *armv8_mode_name(unsigned psr_mode);
323 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
324 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
326 extern void armv8_free_reg_cache(struct target *target);
328 extern const struct command_registration armv8_command_handlers[];
330 #endif /* OPENOCD_TARGET_ARMV8_H */