3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003,2004 Matt Ettus
6 // Copyright (C) 2008 Corgan Enterprises LLC
8 // This program is free software; you can redistribute it and/or modify
9 // it under the terms of the GNU General Public License as published by
10 // the Free Software Foundation; either version 2 of the License, or
11 // (at your option) any later version.
13 // This program is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 // GNU General Public License for more details.
18 // You should have received a copy of the GNU General Public License
19 // along with this program; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
23 // Top level module for a full setup with DUCs and DDCs
25 // Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
26 // for debugging info. NB, This can kill the m'board and/or d'board if you
27 // have anything except basic d'boards installed.
29 // Uncomment the following to include optional circuitry
31 `include "../top/config.vh"
32 `include "../../../../usrp/firmware/include/fpga_regs_common.v"
33 `include "../../../../usrp/firmware/include/fpga_regs_standard.v"
36 (output MYSTERY_SIGNAL,
47 input wire [11:0] rx_a_a,
48 input wire [11:0] rx_b_a,
49 input wire [11:0] rx_a_b,
50 input wire [11:0] rx_b_b,
52 output wire [13:0] tx_a,
53 output wire [13:0] tx_b,
60 input wire [2:0] usbctl,
61 output wire [1:0] usbrdy,
62 inout [15:0] usbdata, // NB Careful, inout
64 // These are the general purpose i/o's that go to the daughterboard slots
65 inout wire [15:0] io_tx_a,
66 inout wire [15:0] io_tx_b,
67 inout wire [15:0] io_rx_a,
68 inout wire [15:0] io_rx_b
70 wire [15:0] debugdata,debugctrl;
71 assign MYSTERY_SIGNAL = 1'b0;
79 wire have_space, have_pkt_rdy;
80 assign usbrdy[0] = have_space;
81 assign usbrdy[1] = have_pkt_rdy;
83 wire tx_underrun, rx_overrun;
84 wire clear_status = FX2_1;
85 assign FX2_2 = rx_overrun;
86 assign FX2_3 = tx_underrun;
88 wire [15:0] usbdata_out;
90 wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
93 wire [3:0] rx_numchan;
94 wire [2:0] tx_numchan;
96 wire [7:0] interp_rate, decim_rate;
97 wire [31:0] tx_debugbus, rx_debugbus;
99 wire enable_tx, enable_rx;
100 wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
103 // Tri-state bus macro
104 bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
106 assign clk64 = master_clk;
108 wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
109 wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
110 wire [15:0] ch0rx_ext,ch1rx_ext;
113 wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;//analog signals
114 wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
116 wire strobe_interp, tx_sample_strobe;
120 wire [6:0] serial_addr;
121 wire [31:0] serial_data;
123 reg [15:0] debug_counter;
124 reg [15:0] loopback_i_0,loopback_q_0;
126 //TX_DIG streaming digital IO signals
127 wire i_out_dig_0,i_out_dig_1,q_out_dig_0,q_out_dig_1;
128 wire rx_dig0_i, rx_dig0_q,rx_dig1_i,rx_dig1_q;
130 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
135 ( .usbclk(usbclk), .bus_reset(tx_bus_reset),
136 .usbdata(usbdata),.WR(WR), .have_space(have_space),
137 .tx_underrun(tx_underrun), .clear_status(clear_status),
138 .txclk(clk64), .reset(tx_dsp_reset),
139 .channels({tx_numchan,1'b0}),
140 .tx_i_0(ch0tx),.tx_q_0(ch1tx),
141 .tx_i_1(ch2tx),.tx_q_1(ch3tx),
142 .txstrobe(strobe_interp),
144 .debugbus(tx_debugbus) );
148 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
149 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
150 .interpolator_strobe(strobe_interp),.freq(),
151 .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0));
153 assign i_out_0=16'd0;
154 assign q_out_0=16'd0;
159 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
160 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
161 .interpolator_strobe(strobe_interp),.freq(),
162 .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
164 assign i_out_1=16'd0;
165 assign q_out_1=16'd0;
170 setting_reg #(`FR_TX_MUX)
171 sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
172 .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
174 wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
175 wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
176 wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
177 wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
179 wire tx_dig_a_a = (dac0mux[1] ? (dac0mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac0mux[0] ? q_out_dig_0 : i_out_dig_0));
180 wire tx_dig_b_a = (dac1mux[1] ? (dac1mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac1mux[0] ? q_out_dig_0 : i_out_dig_0));
181 wire tx_dig_a_b = (dac2mux[1] ? (dac2mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac2mux[0] ? q_out_dig_0 : i_out_dig_0));
182 wire tx_dig_b_b = (dac3mux[1] ? (dac3mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac3mux[0] ? q_out_dig_0 : i_out_dig_0));
184 //wire [1:0] tx_dig_a = {tx_dig_a_a,tx_dig_b_a};
185 //wire [1:0] tx_dig_b = {tx_dig_a_b,tx_dig_b_b};
187 //wire tx_dig_a_chan = (dac0mux[1] | dac1mux[1] );
188 //wire tx_dig_b_chan = (dac2mux[1] | dac3mux[1] );
190 //TODO make enabling tx_dig configurable through register
192 wire enable_tx_dig_a = 1'b1 & enable_tx;
193 wire enable_tx_dig_b = 1'b1 & enable_tx;
195 wire tx_dig_a_a_en = dac0mux[3] & enable_tx_dig_a;
196 wire tx_dig_b_a_en = dac1mux[3] & enable_tx_dig_a;
197 wire tx_dig_a_b_en = dac2mux[3] & enable_tx_dig_b;
198 wire tx_dig_b_b_en = dac3mux[3] & enable_tx_dig_b;
200 //TODO make gpio bits used for tx_dig configurable through register
201 assign io_tx_a_out = {tx_dig_a_a_en?tx_dig_a_a:reg_0[15],tx_dig_b_a_en?tx_dig_b_a:reg_0[14],reg_0[13:0]};
202 assign io_tx_b_out = {tx_dig_a_b_en?tx_dig_a_b:reg_2[15],tx_dig_b_b_en?tx_dig_b_b:reg_2[14],reg_2[13:0]};
203 assign io_tx_a_force_output = {tx_dig_a_a_en,tx_dig_b_a_en,14'b0};
204 assign io_tx_b_force_output = {tx_dig_a_b_en,tx_dig_b_b_en,14'b0};
208 //TODO make enabling tx_dig configurable through register
209 //tx_chain_dig tx_chain_dig_0
210 // ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
211 // .i_in(ch0tx), q_in(ch1tx),
212 // .i_out_ana(bb_tx_i0),
213 // .q_out_ana(bb_tx_q0),
214 // .i_out_dig(i_out_dig_0),
215 // .q_out_dig(q_out_dig_0)
217 tx_chain_dig tx_chain_dig_0
218 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
219 .i_in(ch0tx),.q_in(ch1tx),
220 .i_out_ana(bb_tx_i0),.q_out_ana(bb_tx_q0),
221 .i_out_dig(i_out_dig_0),.q_out_dig(q_out_dig_0));
223 assign bb_tx_i0 = ch0tx;
224 assign bb_tx_q0 = ch1tx;
225 assign i_out_dig_0=1'b0;
226 assign q_out_dig_0=1'b0;
230 //TODO make enabling tx_dig configurable through register
231 tx_chain_dig tx_chain_dig_1
232 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
233 .i_in(ch2tx),.q_in(ch3tx),
234 .i_out_ana(bb_tx_i1),.q_out_ana(bb_tx_q1),
235 .i_out_dig(i_out_dig_1),.q_out_dig(q_out_dig_1));
236 // tx_chain_dig tx_chain_dig_1
237 // ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
238 // .i_in(ch2tx), q_in(ch3tx),
239 // .i_out_ana(bb_tx_i1),
240 // .q_out_ana(bb_tx_q1),
241 // .i_out_dig(i_out_dig_1),
242 // .q_out_dig(q_out_dig_1)
245 assign bb_tx_i1 = ch2tx;
246 assign bb_tx_q1 = ch3tx;
247 assign i_out_dig_1=1'b0;
248 assign q_out_dig_1=1'b0;
251 wire txsync = tx_sample_strobe;
252 assign TXSYNC_A = txsync;
253 assign TXSYNC_B = txsync;
255 assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
256 assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
257 `else // `ifdef TX_ON
258 assign io_tx_a_out = reg_0;
259 assign io_tx_b_out = reg_2;
260 assign io_tx_a_force_output=16'b0;
261 assign io_tx_b_force_output=16'b0;
263 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
266 wire rx_sample_strobe,strobe_decim,hb_strobe;
267 wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
268 bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
270 wire loopback = settings[0];
271 wire counter = settings[1];
273 always @(posedge clk64)
275 debug_counter <= #1 16'd0;
277 debug_counter <= #1 16'd0;
279 debug_counter <=#1 debug_counter + 16'd2;
281 always @(posedge clk64)
284 loopback_i_0 <= #1 ch0tx;
285 loopback_q_0 <= #1 ch1tx;
289 wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
290 wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
292 adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
293 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
294 .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
295 .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
296 .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
297 .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
298 .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
299 .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
302 ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
303 .reset_regs(rx_dsp_reset),
304 .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
305 .channels(rx_numchan),
306 .ch_0(ch0rx_ext),.ch_1(ch1rx_ext),
307 .ch_2(ch2rx),.ch_3(ch3rx),
308 .ch_4(ch4rx),.ch_5(ch5rx),
309 .ch_6(ch6rx),.ch_7(ch7rx),
310 .rxclk(clk64),.rxstrobe(hb_strobe),
311 .clear_status(clear_status),
312 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
313 .debugbus(rx_debugbus) );
316 rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
317 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
318 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
319 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
320 .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
322 assign bb_rx_i0=16'd0;
323 assign bb_rx_q0=16'd0;
327 rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
328 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
329 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
330 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
331 .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
333 assign bb_rx_i1=16'd0;
334 assign bb_rx_q1=16'd0;
338 rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
339 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
340 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
341 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
342 .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
344 assign bb_rx_i2=16'd0;
345 assign bb_rx_q2=16'd0;
349 rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
350 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
351 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
352 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
353 .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
355 assign bb_rx_i3=16'd0;
356 assign bb_rx_q3=16'd0;
360 wire enable_rx_dig = 1'b1 & enable_rx;//TODO make enabling rx_dig configurable through register
361 assign io_rx_a_force_input = {enable_rx_dig,enable_rx_dig,14'b0};
362 assign io_rx_b_force_input = {enable_rx_dig,enable_rx_dig,14'b0};
363 gpio_input gpio_input(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
364 .out_strobe(hb_strobe),
365 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
366 .io_rx_a_in(io_rx_a),.io_rx_b_in(io_rx_b),
367 //.io_tx_a_in(io_tx_a),.io_tx_b_in(io_tx_b),
368 .rx_dig0_i(rx_dig0_i),.rx_dig0_q(rx_dig0_q),
369 .rx_dig1_i(rx_dig1_i),.rx_dig1_q(rx_dig1_q) );
372 rx_chain_dig rx_chain_dig_0
373 ( .clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx_dig),
374 .i_in_ana(bb_rx_i0),.q_in_ana(bb_rx_q0),
375 .i_in_dig(rx_dig0_i),.q_in_dig(rx_dig0_q),
376 .i_out(ch0rx),.q_out(ch1rx));
378 assign ch0rx = bb_rx_i0;
379 assign ch1rx = bb_rx_q0;
382 assign ch0rx_ext = counter ? debug_counter : loopback ? loopback_i_0 : ch0rx;
383 assign ch1rx_ext = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : ch1rx;
386 rx_chain_dig rx_chain_dig_1
387 ( .clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx_dig),
388 .i_in_ana(bb_rx_i1),.q_in_ana(bb_rx_q1),
389 .i_in_dig(rx_dig1_i),.q_in_dig(rx_dig1_q),
390 .i_out(ch2rx),.q_out(ch3rx));
392 assign ch2rx = bb_rx_i1;
393 assign ch3rx = bb_rx_q1;
396 assign ch4rx = bb_rx_i2;
397 assign ch5rx = bb_rx_q2;
398 assign ch6rx = bb_rx_i3;
399 assign ch7rx = bb_rx_q3;
400 `else // `ifdef RX_DIG_ON
401 assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
402 assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
403 assign ch2rx = bb_rx_i1;
404 assign ch3rx = bb_rx_q1;
405 assign ch4rx = bb_rx_i2;
406 assign ch5rx = bb_rx_q2;
407 assign ch6rx = bb_rx_i3;
408 assign ch7rx = bb_rx_q3;
409 `endif // `ifdef RX_DIG_ON
411 `endif // `ifdef RX_ON
413 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
416 wire [31:0] capabilities;
417 assign capabilities[7] = `TX_CAP_HB;
418 assign capabilities[6:4] = `TX_CAP_NCHAN;
419 assign capabilities[3] = `RX_CAP_HB;
420 assign capabilities[2:0] = `RX_CAP_NCHAN;
424 ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
425 .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
426 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
427 .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
428 .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
431 wire [15:0] reg_0,reg_1,reg_2,reg_3;
432 wire [15:0] io_tx_a_out;
433 wire [15:0] io_tx_b_out;
434 wire [15:0] io_tx_a_force_output;
435 wire [15:0] io_tx_b_force_output;
436 wire [15:0] io_rx_a_force_input;
437 wire [15:0] io_rx_b_force_input;
439 master_control master_control
440 ( .master_clk(clk64),.usbclk(usbclk),
441 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
442 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
443 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
444 .enable_tx(enable_tx),.enable_rx(enable_rx),
445 .interp_rate(interp_rate),.decim_rate(decim_rate),
446 .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
447 .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
449 //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
450 .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]),
451 .debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]),
452 //.tx_dig_a(tx_dig_a),tx_dig_b(tx_dig_b),
453 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
456 (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
457 .reg_0(io_tx_a_out),.reg_1(reg_1),.reg_2(io_tx_b_out),.reg_3(reg_3),
458 .io_0_force_output(io_tx_a_force_output), .io_2_force_output(io_tx_b_force_output),
459 .io_1_force_input(io_rx_a_force_input), .io_3_force_input(io_rx_b_force_input),
460 .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
461 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
463 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
465 setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
467 endmodule // usrp_gpio