2 * pic18f4520.h - PIC18F4520 Device Library Header
4 * This file is part of the GNU PIC Library.
7 * The GNU PIC Library is maintained by
8 * Raphael Neider <rneider@web.de>
10 * originally designed by
11 * Vangelis Rokas <vrokas@otenet.gr>
17 #ifndef __PIC18F4520_H__
18 #define __PIC18F4520_H__ 1
20 extern __sfr __at (0xF80) PORTA;
57 extern volatile __PORTA_t __at (0xF80) PORTAbits;
59 extern __sfr __at (0xF81) PORTB;
86 extern volatile __PORTB_t __at (0xF81) PORTBbits;
88 extern __sfr __at (0xF82) PORTC;
135 extern volatile __PORTC_t __at (0xF82) PORTCbits;
137 extern __sfr __at (0xF83) PORTD;
164 extern volatile __PORTD_t __at (0xF83) PORTDbits;
166 extern __sfr __at (0xF84) PORTE;
193 extern volatile __PORTE_t __at (0xF84) PORTEbits;
195 extern __sfr __at (0xF89) LATA;
208 extern volatile __LATA_t __at (0xF89) LATAbits;
210 extern __sfr __at (0xF8A) LATB;
223 extern volatile __LATB_t __at (0xF8A) LATBbits;
225 extern __sfr __at (0xF8B) LATC;
238 extern volatile __LATC_t __at (0xF8B) LATCbits;
240 extern __sfr __at (0xF8C) LATD;
253 extern volatile __LATD_t __at (0xF8C) LATDbits;
255 extern __sfr __at (0xF8D) LATE;
268 extern volatile __LATE_t __at (0xF8D) LATEbits;
270 extern __sfr __at (0xF92) TRISA;
283 extern volatile __TRISA_t __at (0xF92) TRISAbits;
285 extern __sfr __at (0xF93) TRISB;
298 extern volatile __TRISB_t __at (0xF93) TRISBbits;
300 extern __sfr __at (0xF94) TRISC;
313 extern volatile __TRISC_t __at (0xF94) TRISCbits;
315 extern __sfr __at (0xF95) TRISD;
328 extern volatile __TRISD_t __at (0xF95) TRISDbits;
330 extern __sfr __at (0xF96) TRISE;
337 unsigned PSPMODE : 1;
343 extern volatile __TRISE_t __at (0xF96) TRISEbits;
345 extern __sfr __at (0xF9B) OSCTUNE;
351 unsigned HF256DIV : 1;
354 extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
356 extern __sfr __at (0xF9D) PIE1;
369 extern volatile __PIE1_t __at (0xF9D) PIE1bits;
371 extern __sfr __at (0xF9E) PIR1;
384 extern volatile __PIR1_t __at (0xF9E) PIR1bits;
386 extern __sfr __at (0xF9F) IPR1;
399 extern volatile __IPR1_t __at (0xF9F) IPR1bits;
401 extern __sfr __at (0xFA0) PIE2;
414 extern volatile __PIE2_t __at (0xFA0) PIE2bits;
416 extern __sfr __at (0xFA1) PIR2;
429 extern volatile __PIR2_t __at (0xFA1) PIR2bits;
431 extern __sfr __at (0xFA2) IPR2;
444 extern volatile __IPR2_t __at (0xFA2) IPR2bits;
446 extern __sfr __at (0xFA6) EECON1;
459 extern volatile __EECON1_t __at (0xFA6) EECON1bits;
461 extern __sfr __at (0xFA7) EECON2;
463 extern __sfr __at (0xFA8) EEDATA;
465 extern __sfr __at (0xFA9) EEADR;
467 extern __sfr __at (0xFAB) RCSTA;
480 extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
482 extern __sfr __at (0xFAC) TXSTA;
495 extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
497 extern __sfr __at (0xFAD) TXREG;
499 extern __sfr __at (0xFAE) RCREG;
501 extern __sfr __at (0xFAF) SPBRG;
503 extern __sfr __at (0xFB0) SPBRGH;
505 extern __sfr __at (0xFB1) T3CON;
510 unsigned nT3SYNC : 1;
517 extern volatile __T3CON_t __at (0xFB1) T3CONbits;
519 extern __sfr __at (0xFB2) TMR3L;
521 extern __sfr __at (0xFB3) TMR3H;
523 extern __sfr __at (0xFB4) CMCON;
534 extern volatile __CMCON_t __at (0xFB4) CMCONbits;
536 extern __sfr __at (0xFB5) CVRCON;
546 extern volatile __CVRCON_t __at (0xFB5) CVRCONbits;
548 extern __sfr __at (0xFB6) ECCPAS1;
554 unsigned ECCPASE : 1;
557 extern volatile __ECCPAS1_t __at (0xFB6) ECCPAS1bits;
559 extern __sfr __at (0xFB7) PWM1CON;
566 extern volatile __PWM1CON_t __at (0xFB7) PWM1CONbits;
568 extern __sfr __at (0xFB8) BAUDCON;
581 extern volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
583 extern __sfr __at (0xFBA) CCP2CON;
592 extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
594 extern __sfr __at (0xFBB) CCPR2L;
596 extern __sfr __at (0xFBC) CCPR2H;
598 extern __sfr __at (0xFBD) ECCP1CON;
606 extern volatile __ECCP1CON_t __at (0xFBD) ECCP1CONbits;
608 extern __sfr __at (0xFBE) CCPR1L;
610 extern __sfr __at (0xFBF) CCPR1H;
612 extern __sfr __at (0xFC0) ADCON2;
621 extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
623 extern __sfr __at (0xFC1) ADCON1;
632 extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
634 extern __sfr __at (0xFC2) ADCON0;
638 unsigned GO_nDONE : 1;
644 extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
646 extern __sfr __at (0xFC3) ADRESL;
648 extern __sfr __at (0xFC4) ADRESH;
650 extern __sfr __at (0xFC5) SSPCON2;
659 unsigned ACKSTAT : 1;
663 extern volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
665 extern __sfr __at (0xFC6) SSPCON1;
675 extern volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
677 extern __sfr __at (0xFC7) SSPSTAT;
690 extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
692 extern __sfr __at (0xFC8) SSPADD;
694 extern __sfr __at (0xFC9) SSPBUF;
696 extern __sfr __at (0xFCA) T2CON;
705 extern volatile __T2CON_t __at (0xFCA) T2CONbits;
707 extern __sfr __at (0xFCB) PR2;
709 extern __sfr __at (0xFCC) TMR2;
711 extern __sfr __at (0xFCD) T1CON;
716 unsigned nT1SYNC : 1;
717 unsigned T1OSCEN : 1;
723 extern volatile __T1CON_t __at (0xFCD) T1CONbits;
725 extern __sfr __at (0xFCE) TMR1L;
727 extern __sfr __at (0xFCF) TMR1H;
729 extern __sfr __at (0xFD0) RCON;
742 extern volatile __RCON_t __at (0xFD0) RCONbits;
744 extern __sfr __at (0xFD1) WDTCON;
757 extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
759 extern __sfr __at (0xFD2) LVDCON;
769 extern volatile __LVDCON_t __at (0xFD2) LVDCONbits;
771 extern __sfr __at (0xFD3) OSCCON;
781 extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
783 extern __sfr __at (0xFD5) T0CON;
794 extern volatile __T0CON_t __at (0xFD5) T0CONbits;
796 extern __sfr __at (0xFD6) TMR0L;
798 extern __sfr __at (0xFD7) TMR0H;
800 extern __sfr __at (0xFD8) STATUS;
813 extern volatile __STATUS_t __at (0xFD8) STATUSbits;
815 extern __sfr __at (0xFD9) FSR2L;
817 extern __sfr __at (0xFDA) FSR2H;
827 extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
829 extern __sfr __at (0xFDB) PLUSW2;
831 extern __sfr __at (0xFDC) PREINC2;
833 extern __sfr __at (0xFDD) POSTDEC2;
835 extern __sfr __at (0xFDE) POSTINC2;
837 extern __sfr __at (0xFDF) INDF2;
839 extern __sfr __at (0xFE0) BSR;
849 extern volatile __BSR_t __at (0xFE0) BSRbits;
851 extern __sfr __at (0xFE1) FSR1L;
853 extern __sfr __at (0xFE2) FSR1H;
863 extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
865 extern __sfr __at (0xFE3) PLUSW1;
867 extern __sfr __at (0xFE4) PREINC1;
869 extern __sfr __at (0xFE5) POSTDEC1;
871 extern __sfr __at (0xFE6) POSTINC1;
873 extern __sfr __at (0xFE7) INDF1;
875 extern __sfr __at (0xFE8) WREG;
877 extern __sfr __at (0xFE9) FSR0L;
879 extern __sfr __at (0xFEA) FSR0H;
889 extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
891 extern __sfr __at (0xFEB) PLUSW0;
893 extern __sfr __at (0xFEC) PREINC0;
895 extern __sfr __at (0xFED) POSTDEC0;
897 extern __sfr __at (0xFEE) POSTINC0;
899 extern __sfr __at (0xFEF) INDF0;
901 extern __sfr __at (0xFF0) INTCON3;
914 extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
916 extern __sfr __at (0xFF1) INTCON2;
923 unsigned INTEDG2 : 1;
924 unsigned INTEDG1 : 1;
925 unsigned INTEDG0 : 1;
929 extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
931 extern __sfr __at (0xFF2) INTCON;
940 unsigned PEIE_GIEL : 1;
941 unsigned GIE_GIEH : 1;
964 extern volatile __INTCON_t __at (0xFF2) INTCONbits;
966 extern __sfr __at (0xFF3) PRODL;
968 extern __sfr __at (0xFF4) PRODH;
970 extern __sfr __at (0xFF5) TABLAT;
972 extern __sfr __at (0xFF6) TBLPTRL;
974 extern __sfr __at (0xFF7) TBLPTRH;
976 extern __sfr __at (0xFF8) TBLPTRU;
979 unsigned TBLPTRU : 5;
985 extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
987 extern __sfr __at (0xFF9) PCL;
989 extern __sfr __at (0xFFA) PCLATH;
995 extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
997 extern __sfr __at (0xFFB) PCLATU;
1006 extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
1008 extern __sfr __at (0xFFC) STKPTR;
1011 unsigned STKPTR : 5;
1013 unsigned STKUNF : 1;
1014 unsigned STKFUL : 1;
1017 extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
1019 extern __sfr __at (0xFFD) TOSL;
1021 extern __sfr __at (0xFFE) TOSH;
1023 extern __sfr __at (0xFFF) TOSU;
1032 extern volatile __TOSU_t __at (0xFFF) TOSUbits;
1034 /* Configuration register locations */
1035 #define CONFIG1H 0x300001
1036 #define CONFIG2L 0x300002
1037 #define CONFIG2H 0x300003
1038 #define CONFIG3H 0x300005
1039 #define CONFIG4L 0x300006
1040 #define CONFIG5L 0x300008
1041 #define CONFIG5H 0x300009
1042 #define CONFIG6L 0x30000A
1043 #define CONFIG6H 0x30000B
1044 #define CONFIG7L 0x30000C
1045 #define CONFIG7H 0x30000D
1048 /* Oscillator 1H options */
1049 #define _OSC_11XX_EXT_RC_CLKOUT_ON_RA6_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
1050 #define _OSC_101X_EXT_RC_CLKOUT_ON_RA6_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
1051 #define _OSC_INT_RC_CLKOUT_ON_RA6_PORT_ON_RA7_1H 0xF9 /* INT RC-CLKOUT on RA6,Port on RA7 */
1052 #define _OSC_INT_RC_PORT_ON_RA6_PORT_ON_RA7_1H 0xF8 /* INT RC-Port on RA6,Port on RA7 */
1053 #define _OSC_EXT_RC_PORT_ON_RA6_1H 0xF7 /* EXT RC-Port on RA6 */
1054 #define _OSC_HS_PLL_ON_FREQ_4XFOSC1_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
1055 #define _OSC_EC_PORT_ON_RA6_1H 0xF5 /* EC-Port on RA6 */
1056 #define _OSC_EC_CLKOUT_ON_RA6_1H 0xF4 /* EC-CLKOUT on RA6 */
1057 #define _OSC_0011_EXT_RC_CLKOUT_ON_RA6_1H 0xF3 /* 0011 EXT RC-CLKOUT on RA6 */
1058 #define _OSC_HS_1H 0xF2 /* HS */
1059 #define _OSC_XT_1H 0xF1 /* XT */
1060 #define _OSC_LP_1H 0xF0 /* LP */
1062 /* Fail-Safe Clock Monitor Enable 1H options */
1063 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1064 #define _FCMEN_ON_1H 0xFF /* Enabled */
1066 /* Internal External Switch Over Mode 1H options */
1067 #define _IESO_OFF_1H 0x7F /* Disabled */
1068 #define _IESO_ON_1H 0xFF /* Enabled */
1071 /* Power Up Timer 2L options */
1072 #define _PUT_OFF_2L 0xFF /* Disabled */
1073 #define _PUT_ON_2L 0xFE /* Enabled */
1075 /* Brown Out Detect 2L options */
1076 #define _BODEN_ON_2L 0xFF /* Enabled in hardware, SBOREN disabled */
1077 #define _BODEN_ON_WHILE_ACTIVE_2L 0xFD /* Enabled while active,disabled in SLEEP,SBOREN disabled */
1078 #define _BODEN_CONTROLLED_WITH_SBOREN_BIT_2L 0xFB /* Controlled with SBOREN bit */
1079 #define _BODEN_OFF_2L 0xF9 /* Disabled in hardware, SBOREN disabled */
1081 /* Brown Out Voltage 2L options */
1082 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
1083 #define _BODENV_2_7V_2L 0xF7 /* 2.7V */
1084 #define _BODENV_4_2V_2L 0xEF /* 4.2V */
1085 #define _BODENV_4_5V_2L 0xE7 /* 4.5V */
1088 /* Watchdog Timer 2H options */
1089 #define _WDT_ON_2H 0xFF /* Enabled */
1090 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1092 /* Watchdog Postscaler 2H options */
1093 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1094 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1095 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1096 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1097 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1098 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1099 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1100 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1101 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1102 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1103 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1104 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1105 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1106 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1107 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1108 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1111 /* CCP2 Mux 3H options */
1112 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1113 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1115 /* PortB A/D Enable 3H options */
1116 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET_3H 0xFF /* PORTB<4:0> configured as analog inputs on RESET */
1117 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H 0xFD /* PORTB<4:0> configured as digital I/O on RESET */
1119 /* Low Power Timer1 Osc enable 3H options */
1120 #define _LPT1OSC_ON_3H 0xFF /* Enabled */
1121 #define _LPT1OSC_OFF_3H 0xFB /* Disabled */
1123 /* Master Clear Enable 3H options */
1124 #define _MCLRE_MCLR_ON_RE3_OFF_3H 0xFF /* MCLR Enabled,RE3 Disabled */
1125 #define _MCLRE_MCLR_OFF_RE3_ON_3H 0x7F /* MCLR Disabled,RE3 Enabled */
1128 /* Stack Overflow Reset 4L options */
1129 #define _STVR_ON_4L 0xFF /* Enabled */
1130 #define _STVR_OFF_4L 0xFE /* Disabled */
1132 /* Low Voltage Program 4L options */
1133 #define _LVP_ON_4L 0xFF /* Enabled */
1134 #define _LVP_OFF_4L 0xFB /* Disabled */
1136 /* Extended CPU Enable 4L options */
1137 #define _ENHCPU_ON_4L 0xFF /* Enabled */
1138 #define _ENHCPU_OFF_4L 0xBF /* Disabled */
1140 /* Background Debug 4L options */
1141 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1142 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1145 /* Code Protect 00800-01FFF 5L options */
1146 #define _CP_0_OFF_5L 0xFF /* Disabled */
1147 #define _CP_0_ON_5L 0xFE /* Enabled */
1149 /* Code Protect 02000-03FFF 5L options */
1150 #define _CP_1_OFF_5L 0xFF /* Disabled */
1151 #define _CP_1_ON_5L 0xFD /* Enabled */
1153 /* Code Protect 04000-05FFF 5L options */
1154 #define _CP_2_OFF_5L 0xFF /* Disabled */
1155 #define _CP_2_ON_5L 0xFB /* Enabled */
1157 /* Code Protect 06000-07FFF 5L options */
1158 #define _CP_3_OFF_5L 0xFF /* Disabled */
1159 #define _CP_3_ON_5L 0xF7 /* Enabled */
1162 /* Data EEPROM Code Protect 5H options */
1163 #define _CPD_OFF_5H 0xFF /* Disabled */
1164 #define _CPD_ON_5H 0x7F /* Enabled */
1166 /* Code Protect Boot 5H options */
1167 #define _CPB_OFF_5H 0xFF /* Disabled */
1168 #define _CPB_ON_5H 0xBF /* Enabled */
1171 /* Table Write Protect 00800-01FFF 6L options */
1172 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1173 #define _WRT_0_ON_6L 0xFE /* Enabled */
1175 /* Table Write Protect 02000-03FFF 6L options */
1176 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1177 #define _WRT_1_ON_6L 0xFD /* Enabled */
1179 /* Table Write Protect 04000-05FFF 6L options */
1180 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1181 #define _WRT_2_ON_6L 0xFB /* Enabled */
1183 /* Table Write Protect 06000-07FFF 6L options */
1184 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1185 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1188 /* Data EEPROM Write Protect 6H options */
1189 #define _WRTD_OFF_6H 0xFF /* Disabled */
1190 #define _WRTD_ON_6H 0x7F /* Enabled */
1192 /* Table Write Protect Boot 6H options */
1193 #define _WRTB_OFF_6H 0xFF /* Disabled */
1194 #define _WRTB_ON_6H 0xBF /* Enabled */
1196 /* Config. Write Protect 6H options */
1197 #define _WRTC_OFF_6H 0xFF /* Disabled */
1198 #define _WRTC_ON_6H 0xDF /* Enabled */
1201 /* Table Read Protect 00800-01FFF 7L options */
1202 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1203 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1205 /* Table Read Protect 02000-03FFF 7L options */
1206 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1207 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1209 /* Table Read Protect 04000-05FFF 7L options */
1210 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1211 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1213 /* Table Read Protect 06000-07FFF 7L options */
1214 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1215 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1218 /* Table Read Protect Boot 7H options */
1219 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1220 #define _EBTRB_ON_7H 0xBF /* Enabled */
1224 /* Location of User ID words */
1225 #define __IDLOC0 0x200000
1226 #define __IDLOC1 0x200001
1227 #define __IDLOC2 0x200002
1228 #define __IDLOC3 0x200003
1229 #define __IDLOC4 0x200004
1230 #define __IDLOC5 0x200005
1231 #define __IDLOC6 0x200006
1232 #define __IDLOC7 0x200007
1234 #endif // __PIC18F4520__