3 * pic18f452.h - PIC18F452 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F452_H__
16 #define __PIC18F452_H__
18 extern __sfr __at 0xf80 PORTA;
65 extern volatile __PORTAbits_t __at 0xf80 PORTAbits;
67 extern __sfr __at 0xf81 PORTB;
92 extern volatile __PORTBbits_t __at 0xf81 PORTBbits;
94 extern __sfr __at 0xf82 PORTC;
130 extern volatile __PORTCbits_t __at 0xf82 PORTCbits;
132 extern __sfr __at 0xf83 PORTD;
157 extern volatile __PORTDbits_t __at 0xf83 PORTDbits;
159 extern __sfr __at 0xf84 PORTE;
195 extern volatile __PORTEbits_t __at 0xf84 PORTEbits;
197 extern __sfr __at 0xf89 LATA;
211 extern volatile __LATAbits_t __at 0xf89 LATAbits;
213 extern __sfr __at 0xf8a LATB;
227 extern volatile __LATBbits_t __at 0xf8a LATBbits;
229 extern __sfr __at 0xf8b LATC;
243 extern volatile __LATCbits_t __at 0xf8b LATCbits;
245 extern __sfr __at 0xf8c LATD;
259 extern volatile __LATDbits_t __at 0xf8c LATDbits;
261 extern __sfr __at 0xf8d LATE;
275 extern volatile __LATEbits_t __at 0xf8d LATEbits;
277 extern __sfr __at 0xf92 TRISA;
291 extern volatile __TRISAbits_t __at 0xf92 TRISAbits;
293 extern __sfr __at 0xf93 TRISB;
307 extern volatile __TRISBbits_t __at 0xf93 TRISBbits;
309 extern __sfr __at 0xf94 TRISC;
323 extern volatile __TRISCbits_t __at 0xf94 TRISCbits;
325 extern __sfr __at 0xf95 TRISD;
339 extern volatile __TRISDbits_t __at 0xf95 TRISDbits;
341 extern __sfr __at 0xf96 TRISE;
355 extern volatile __TRISEbits_t __at 0xf96 TRISEbits;
357 extern __sfr __at 0xf9d PIE1;
371 extern volatile __PIE1bits_t __at 0xf9d PIE1bits;
373 extern __sfr __at 0xf9e PIR1;
387 extern volatile __PIR1bits_t __at 0xf9e PIR1bits;
389 extern __sfr __at 0xf9f IPR1;
403 extern volatile __IPR1bits_t __at 0xf9f IPR1bits;
405 extern __sfr __at 0xfa0 PIE2;
419 extern volatile __PIE2bits_t __at 0xfa0 PIE2bits;
421 extern __sfr __at 0xfa1 PIR2;
435 extern volatile __PIR2bits_t __at 0xfa1 PIR2bits;
437 extern __sfr __at 0xfa2 IPR2;
451 extern volatile __IPR2bits_t __at 0xfa2 IPR2bits;
453 extern __sfr __at 0xfa6 EECON1;
467 extern volatile __EECON1bits_t __at 0xfa6 EECON1bits;
469 extern __sfr __at 0xfa7 EECON2;
470 extern __sfr __at 0xfa8 EEDATA;
471 extern __sfr __at 0xfa9 EEADR;
472 extern __sfr __at 0xfab RCSTA;
486 extern volatile __RCSTAbits_t __at 0xfab RCSTAbits;
488 extern __sfr __at 0xfac TXSTA;
502 extern volatile __TXSTAbits_t __at 0xfac TXSTAbits;
504 extern __sfr __at 0xfad TXREG;
505 extern __sfr __at 0xfae RCREG;
506 extern __sfr __at 0xfaf SPBRG;
507 extern __sfr __at 0xfb1 T3CON;
521 extern volatile __T3CONbits_t __at 0xfb1 T3CONbits;
523 extern __sfr __at 0xfb2 TMR3L;
524 extern __sfr __at 0xfb3 TMR3H;
525 extern __sfr __at 0xfba CCP2CON;
539 extern volatile __CCP2CONbits_t __at 0xfba CCP2CONbits;
541 extern __sfr __at 0xfbb CCPR2L;
542 extern __sfr __at 0xfbc CCPR2H;
543 extern __sfr __at 0xfbd CCP1CON;
557 extern volatile __CCP1CONbits_t __at 0xfbd CCP1CONbits;
559 extern __sfr __at 0xfbe CCPR1L;
560 extern __sfr __at 0xfbf CCPR1H;
561 extern __sfr __at 0xfc1 ADCON1;
575 extern volatile __ADCON1bits_t __at 0xfc1 ADCON1bits;
577 extern __sfr __at 0xfc2 ADCON0;
591 extern volatile __ADCON0bits_t __at 0xfc2 ADCON0bits;
593 extern __sfr __at 0xfc3 ADRESL;
594 extern __sfr __at 0xfc4 ADRESH;
595 extern __sfr __at 0xfc5 SSPCON2;
609 extern volatile __SSPCON2bits_t __at 0xfc5 SSPCON2bits;
611 extern __sfr __at 0xfc6 SSPCON1;
625 extern volatile __SSPCON1bits_t __at 0xfc6 SSPCON1bits;
627 extern __sfr __at 0xfc7 SSPSTAT;
641 extern volatile __SSPSTATbits_t __at 0xfc7 SSPSTATbits;
643 extern __sfr __at 0xfc8 SSPADD;
644 extern __sfr __at 0xfc9 SSPBUF;
645 extern __sfr __at 0xfca T2CON;
659 extern volatile __T2CONbits_t __at 0xfca T2CONbits;
661 extern __sfr __at 0xfcb PR2;
662 extern __sfr __at 0xfcc TMR2;
663 extern __sfr __at 0xfcd T1CON;
668 unsigned NOT_T1SYNC:1;
677 extern volatile __T1CONbits_t __at 0xfcd T1CONbits;
679 extern __sfr __at 0xfce TMR1L;
680 extern __sfr __at 0xfcf TMR1H;
681 extern __sfr __at 0xfd0 RCON;
695 extern volatile __RCONbits_t __at 0xfd0 RCONbits;
697 extern __sfr __at 0xfd1 WDTCON;
722 extern volatile __WDTCONbits_t __at 0xfd1 WDTCONbits;
724 extern __sfr __at 0xfd2 LVDCON;
749 extern volatile __LVDCONbits_t __at 0xfd2 LVDCONbits;
751 extern __sfr __at 0xfd3 OSCCON;
765 extern volatile __OSCCONbits_t __at 0xfd3 OSCCONbits;
767 extern __sfr __at 0xfd5 T0CON;
781 extern volatile __T0CONbits_t __at 0xfd5 T0CONbits;
783 extern __sfr __at 0xfd6 TMR0L;
784 extern __sfr __at 0xfd7 TMR0H;
785 extern __sfr __at 0xfd8 STATUS;
799 extern volatile __STATUSbits_t __at 0xfd8 STATUSbits;
801 extern __sfr __at 0xfd9 FSR2L;
802 extern __sfr __at 0xfda FSR2H;
803 extern __sfr __at 0xfdb PLUSW2;
804 extern __sfr __at 0xfdc PREINC2;
805 extern __sfr __at 0xfdd POSTDEC2;
806 extern __sfr __at 0xfde POSTINC2;
807 extern __sfr __at 0xfdf INDF2;
808 extern __sfr __at 0xfe0 BSR;
809 extern __sfr __at 0xfe1 FSR1L;
810 extern __sfr __at 0xfe2 FSR1H;
811 extern __sfr __at 0xfe3 PLUSW1;
812 extern __sfr __at 0xfe4 PREINC1;
813 extern __sfr __at 0xfe5 POSTDEC1;
814 extern __sfr __at 0xfe6 POSTINC1;
815 extern __sfr __at 0xfe7 INDF1;
816 extern __sfr __at 0xfe8 WREG;
817 extern __sfr __at 0xfe9 FSR0L;
818 extern __sfr __at 0xfea FSR0H;
819 extern __sfr __at 0xfeb PLUSW0;
820 extern __sfr __at 0xfec PREINC0;
821 extern __sfr __at 0xfed POSTDEC0;
822 extern __sfr __at 0xfee POSTINC0;
823 extern __sfr __at 0xfef INDF0;
824 extern __sfr __at 0xff0 INTCON3;
849 extern volatile __INTCON3bits_t __at 0xff0 INTCON3bits;
851 extern __sfr __at 0xff1 INTCON2;
865 extern volatile __INTCON2bits_t __at 0xff1 INTCON2bits;
867 extern __sfr __at 0xff2 INTCON;
881 extern volatile __INTCONbits_t __at 0xff2 INTCONbits;
883 extern __sfr __at 0xff3 PRODL;
884 extern __sfr __at 0xff4 PRODH;
885 extern __sfr __at 0xff5 TABLAT;
886 extern __sfr __at 0xff6 TBLPTRL;
887 extern __sfr __at 0xff7 TBLPTRH;
888 extern __sfr __at 0xff8 TBLPTRU;
889 extern __sfr __at 0xff9 PCL;
890 extern __sfr __at 0xffa PCLATH;
891 extern __sfr __at 0xffb PCLATU;
892 extern __sfr __at 0xffc STKPTR;
906 extern volatile __STKPTRbits_t __at 0xffc STKPTRbits;
908 extern __sfr __at 0xffd TOSL;
909 extern __sfr __at 0xffe TOSH;
910 extern __sfr __at 0xfff TOSU;
913 /* Configuration registers locations */
914 #define __CONFIG1H 0x300001
915 #define __CONFIG2L 0x300002
916 #define __CONFIG2H 0x300003
917 #define __CONFIG3H 0x300005
918 #define __CONFIG4L 0x300006
919 #define __CONFIG5L 0x300008
920 #define __CONFIG5H 0x300009
921 #define __CONFIG6L 0x30000A
922 #define __CONFIG6H 0x30000B
923 #define __CONFIG7L 0x30000C
924 #define __CONFIG7H 0x30000D
928 /* Oscillator 1H options */
929 #define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */
930 #define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */
931 #define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */
932 #define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */
933 #define _OSC_RC_1H 0xFB /* RC */
934 #define _OSC_HS_1H 0xFA /* HS */
935 #define _OSC_XT_1H 0xF9 /* XT */
936 #define _OSC_LP_1H 0xF8 /* LP */
938 /* Osc. Switch Enable 1H options */
939 #define _OSCS_OFF_1H 0xFF /* Disabled */
940 #define _OSCS_ON_1H 0xDF /* Enabled */
942 /* Power Up Timer 2L options */
943 #define _PUT_OFF_2L 0xFF /* Disabled */
944 #define _PUT_ON_2L 0xFE /* Enabled */
946 /* Brown Out Detect 2L options */
947 #define _BODEN_ON_2L 0xFF /* Enabled */
948 #define _BODEN_OFF_2L 0xFD /* Disabled */
950 /* Brown Out Voltage 2L options */
951 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
952 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
953 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
954 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
956 /* Watchdog Timer 2H options */
957 #define _WDT_ON_2H 0xFF /* Enabled */
958 #define _WDT_OFF_2H 0xFE /* Disabled */
960 /* Watchdog Postscaler 2H options */
961 #define _WDTPS_1_128_2H 0xFF /* 1:128 */
962 #define _WDTPS_1_64_2H 0xFD /* 1:64 */
963 #define _WDTPS_1_32_2H 0xFB /* 1:32 */
964 #define _WDTPS_1_16_2H 0xF9 /* 1:16 */
965 #define _WDTPS_1_8_2H 0xF7 /* 1:8 */
966 #define _WDTPS_1_4_2H 0xF5 /* 1:4 */
967 #define _WDTPS_1_2_2H 0xF3 /* 1:2 */
968 #define _WDTPS_1_1_2H 0xF1 /* 1:1 */
970 /* CCP2 Mux 3H options */
971 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
972 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
974 /* Low Voltage Program 4L options */
975 #define _LVP_ON_4L 0xFF /* Enabled */
976 #define _LVP_OFF_4L 0xFB /* Disabled */
978 /* Background Debug 4L options */
979 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
980 #define _BACKBUG_ON_4L 0x7F /* Enabled */
982 /* Stack Overflow Reset 4L options */
983 #define _STVR_ON_4L 0xFF /* Enabled */
984 #define _STVR_OFF_4L 0xFE /* Disabled */
986 /* Code Protect 00200-01FFF 5L options */
987 #define _CP_0_OFF_5L 0xFF /* Disabled */
988 #define _CP_0_ON_5L 0xFE /* Enabled */
990 /* Code Protect 02000-03FFF 5L options */
991 #define _CP_1_OFF_5L 0xFF /* Disabled */
992 #define _CP_1_ON_5L 0xFD /* Enabled */
994 /* Code Protect 04000-05FFF 5L options */
995 #define _CP_2_OFF_5L 0xFF /* Disabled */
996 #define _CP_2_ON_5L 0xFB /* Enabled */
998 /* Code Protect 06000-07FFF 5L options */
999 #define _CP_3_OFF_5L 0xFF /* Disabled */
1000 #define _CP_3_ON_5L 0xF7 /* Enabled */
1002 /* Data EE Read Protect 5H options */
1003 #define _CPD_OFF_5H 0xFF /* Disabled */
1004 #define _CPD_ON_5H 0x7F /* Enabled */
1006 /* Code Protect Boot 5H options */
1007 #define _CPB_OFF_5H 0xFF /* Disabled */
1008 #define _CPB_ON_5H 0xBF /* Enabled */
1010 /* Table Write Protect 00200-01FFF 6L options */
1011 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1012 #define _WRT_0_ON_6L 0xFE /* Enabled */
1014 /* Table Write Protect 02000-03FFF 6L options */
1015 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1016 #define _WRT_1_ON_6L 0xFD /* Enabled */
1018 /* Table Write Protect 04000-05FFF 6L options */
1019 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1020 #define _WRT_2_ON_6L 0xFB /* Enabled */
1022 /* Table Write Protect 06000-07FFF 6L options */
1023 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1024 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1026 /* Data EE Write Protect 6H options */
1027 #define _WRTD_OFF_6H 0xFF /* Disabled */
1028 #define _WRTD_ON_6H 0x7F /* Enabled */
1030 /* Table Write Protect Boot 6H options */
1031 #define _WRTB_OFF_6H 0xFF /* Disabled */
1032 #define _WRTB_ON_6H 0xBF /* Enabled */
1034 /* Config. Write Protect 6H options */
1035 #define _WRTC_OFF_6H 0xFF /* Disabled */
1036 #define _WRTC_ON_6H 0xDF /* Enabled */
1038 /* Table Read Protect 00200-01FFF 7L options */
1039 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1040 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1042 /* Table Read Protect 02000-03FFF 7L options */
1043 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1044 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1046 /* Table Read Protect 04000-05FFF 7L options */
1047 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1048 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1050 /* Table Read Protect 06000-07FFF 7L options */
1051 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1052 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1054 /* Table Read Protect Boot 7H options */
1055 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1056 #define _EBTRB_ON_7H 0xBF /* Enabled */
1059 /* Device ID locations */
1060 #define __IDLOC0 0x200000
1061 #define __IDLOC1 0x200001
1062 #define __IDLOC2 0x200002
1063 #define __IDLOC3 0x200003
1064 #define __IDLOC4 0x200004
1065 #define __IDLOC5 0x200005
1066 #define __IDLOC6 0x200006
1067 #define __IDLOC7 0x200007