2 * pic18f2550.h - PIC18F2550 Device Library Header
4 * This file is part of the GNU PIC Library.
7 * The GNU PIC Library is maintained by
8 * Raphael Neider <rneider@web.de>
10 * originally designed by
11 * Vangelis Rokas <vrokas@otenet.gr>
17 #ifndef __PIC18F2550_H__
18 #define __PIC18F2550_H__ 1
20 extern __sfr __at 0xF62 SPPDATA;
26 extern volatile __SPPDATA_t __at 0xF62 SPPDATAbits;
28 extern __sfr __at 0xF63 SPPCFG;
37 extern volatile __SPPCFG_t __at 0xF63 SPPCFGbits;
39 extern __sfr __at 0xF64 SPPEPS;
49 extern volatile __SPPEPS_t __at 0xF64 SPPEPSbits;
51 extern __sfr __at 0xF65 SPPCON;
64 extern volatile __SPPCON_t __at 0xF65 SPPCONbits;
66 extern __sfr __at 0xF66 UFRML;
72 extern volatile __UFRML_t __at 0xF66 UFRMLbits;
74 extern __sfr __at 0xF67 UFRMH;
85 extern volatile __UFRMH_t __at 0xF67 UFRMHbits;
87 extern __sfr __at 0xF68 UIR;
100 extern volatile __UIR_t __at 0xF68 UIRbits;
102 extern __sfr __at 0xF69 UIE;
107 unsigned ACTIVIE : 1;
110 unsigned STALLIE : 1;
115 extern volatile __UIE_t __at 0xF69 UIEbits;
117 extern __sfr __at 0xF6A UEIR;
122 unsigned CRC16EF : 1;
130 extern volatile __UEIR_t __at 0xF6A UEIRbits;
132 extern __sfr __at 0xF6B UEIE;
137 unsigned CRC16EE : 1;
145 extern volatile __UEIE_t __at 0xF6B UEIEbits;
147 extern __sfr __at 0xF6C USTAT;
157 extern volatile __USTAT_t __at 0xF6C USTATbits;
159 extern __sfr __at 0xF6D UCON;
172 extern volatile __UCON_t __at 0xF6D UCONbits;
174 extern __sfr __at 0xF6E UADDR;
181 extern volatile __UADDR_t __at 0xF6E UADDRbits;
183 extern __sfr __at 0xF6F UCFG;
195 extern volatile __UCFG_t __at 0xF6F UCFGbits;
197 extern __sfr __at 0xF70 UEP0;
200 unsigned EPSTALL : 1;
202 unsigned EPOUTEN : 1;
203 unsigned EPCONDIS : 1;
210 extern volatile __UEP0_t __at 0xF70 UEP0bits;
212 extern __sfr __at 0xF71 UEP1;
215 unsigned EPSTALL : 1;
217 unsigned EPOUTEN : 1;
218 unsigned EPCONDIS : 1;
225 extern volatile __UEP1_t __at 0xF71 UEP1bits;
227 extern __sfr __at 0xF72 UEP2;
230 unsigned EPSTALL : 1;
232 unsigned EPOUTEN : 1;
233 unsigned EPCONDIS : 1;
240 extern volatile __UEP2_t __at 0xF72 UEP2bits;
242 extern __sfr __at 0xF73 UEP3;
245 unsigned EPSTALL : 1;
247 unsigned EPOUTEN : 1;
248 unsigned EPCONDIS : 1;
255 extern volatile __UEP3_t __at 0xF73 UEP3bits;
257 extern __sfr __at 0xF74 UEP4;
260 unsigned EPSTALL : 1;
262 unsigned EPOUTEN : 1;
263 unsigned EPCONDIS : 1;
270 extern volatile __UEP4_t __at 0xF74 UEP4bits;
272 extern __sfr __at 0xF75 UEP5;
275 unsigned EPSTALL : 1;
277 unsigned EPOUTEN : 1;
278 unsigned EPCONDIS : 1;
285 extern volatile __UEP5_t __at 0xF75 UEP5bits;
287 extern __sfr __at 0xF76 UEP6;
290 unsigned EPSTALL : 1;
292 unsigned EPOUTEN : 1;
293 unsigned EPCONDIS : 1;
300 extern volatile __UEP6_t __at 0xF76 UEP6bits;
302 extern __sfr __at 0xF77 UEP7;
305 unsigned EPSTALL : 1;
307 unsigned EPOUTEN : 1;
308 unsigned EPCONDIS : 1;
315 extern volatile __UEP7_t __at 0xF77 UEP7bits;
317 extern __sfr __at 0xF78 UEP8;
320 unsigned EPSTALL : 1;
322 unsigned EPOUTEN : 1;
323 unsigned EPCONDIS : 1;
330 extern volatile __UEP8_t __at 0xF78 UEP8bits;
332 extern __sfr __at 0xF79 UEP9;
335 unsigned EPSTALL : 1;
337 unsigned EPOUTEN : 1;
338 unsigned EPCONDIS : 1;
345 extern volatile __UEP9_t __at 0xF79 UEP9bits;
347 extern __sfr __at 0xF7A UEP10;
350 unsigned EPSTALL : 1;
352 unsigned EPOUTEN : 1;
353 unsigned EPCONDIS : 1;
360 extern volatile __UEP10_t __at 0xF7A UEP10bits;
362 extern __sfr __at 0xF7B UEP11;
365 unsigned EPSTALL : 1;
367 unsigned EPOUTEN : 1;
368 unsigned EPCONDIS : 1;
375 extern volatile __UEP11_t __at 0xF7B UEP11bits;
377 extern __sfr __at 0xF7C UEP12;
380 unsigned EPSTALL : 1;
382 unsigned EPOUTEN : 1;
383 unsigned EPCONDIS : 1;
390 extern volatile __UEP12_t __at 0xF7C UEP12bits;
392 extern __sfr __at 0xF7D UEP13;
395 unsigned EPSTALL : 1;
397 unsigned EPOUTEN : 1;
398 unsigned EPCONDIS : 1;
405 extern volatile __UEP13_t __at 0xF7D UEP13bits;
407 extern __sfr __at 0xF7E UEP14;
410 unsigned EPSTALL : 1;
412 unsigned EPOUTEN : 1;
413 unsigned EPCONDIS : 1;
420 extern volatile __UEP14_t __at 0xF7E UEP14bits;
422 extern __sfr __at 0xF7F UEP15;
425 unsigned EPSTALL : 1;
427 unsigned EPOUTEN : 1;
428 unsigned EPCONDIS : 1;
435 extern volatile __UEP15_t __at 0xF7F UEP15bits;
437 extern __sfr __at 0xF80 PORTA;
474 extern volatile __PORTA_t __at 0xF80 PORTAbits;
476 extern __sfr __at 0xF81 PORTB;
503 extern volatile __PORTB_t __at 0xF81 PORTBbits;
505 extern __sfr __at 0xF82 PORTC;
552 extern volatile __PORTC_t __at 0xF82 PORTCbits;
554 extern __sfr __at 0xF84 PORTE;
581 extern volatile __PORTE_t __at 0xF84 PORTEbits;
583 extern __sfr __at 0xF89 LATA;
596 extern volatile __LATA_t __at 0xF89 LATAbits;
598 extern __sfr __at 0xF8A LATB;
611 extern volatile __LATB_t __at 0xF8A LATBbits;
613 extern __sfr __at 0xF8B LATC;
626 extern volatile __LATC_t __at 0xF8B LATCbits;
628 extern __sfr __at 0xF92 TRISA;
641 extern volatile __TRISA_t __at 0xF92 TRISAbits;
643 extern __sfr __at 0xF93 TRISB;
656 extern volatile __TRISB_t __at 0xF93 TRISBbits;
658 extern __sfr __at 0xF94 TRISC;
671 extern volatile __TRISC_t __at 0xF94 TRISCbits;
673 extern __sfr __at 0xF9B OSCTUNE;
679 unsigned HF256DIV : 1;
682 extern volatile __OSCTUNE_t __at 0xF9B OSCTUNEbits;
684 extern __sfr __at 0xF9D PIE1;
697 extern volatile __PIE1_t __at 0xF9D PIE1bits;
699 extern __sfr __at 0xF9E PIR1;
712 extern volatile __PIR1_t __at 0xF9E PIR1bits;
714 extern __sfr __at 0xF9F IPR1;
727 extern volatile __IPR1_t __at 0xF9F IPR1bits;
729 extern __sfr __at 0xFA0 PIE2;
742 extern volatile __PIE2_t __at 0xFA0 PIE2bits;
744 extern __sfr __at 0xFA1 PIR2;
757 extern volatile __PIR2_t __at 0xFA1 PIR2bits;
759 extern __sfr __at 0xFA2 IPR2;
772 extern volatile __IPR2_t __at 0xFA2 IPR2bits;
774 extern __sfr __at 0xFA6 EECON1;
787 extern volatile __EECON1_t __at 0xFA6 EECON1bits;
789 extern __sfr __at 0xFA7 EECON2;
791 extern __sfr __at 0xFA8 EEDATA;
793 extern __sfr __at 0xFA9 EEADR;
795 extern __sfr __at 0xFAB RCSTA;
808 extern volatile __RCSTA_t __at 0xFAB RCSTAbits;
810 extern __sfr __at 0xFAC TXSTA;
823 extern volatile __TXSTA_t __at 0xFAC TXSTAbits;
825 extern __sfr __at 0xFAD TXREG;
827 extern __sfr __at 0xFAE RCREG;
829 extern __sfr __at 0xFAF SPBRG;
831 extern __sfr __at 0xFB0 SPBRGH;
833 extern __sfr __at 0xFB1 T3CON;
838 unsigned nT3SYNC : 1;
845 extern volatile __T3CON_t __at 0xFB1 T3CONbits;
847 extern __sfr __at 0xFB2 TMR3L;
849 extern __sfr __at 0xFB3 TMR3H;
851 extern __sfr __at 0xFB4 CMCON;
862 extern volatile __CMCON_t __at 0xFB4 CMCONbits;
864 extern __sfr __at 0xFB5 CVRCON;
874 extern volatile __CVRCON_t __at 0xFB5 CVRCONbits;
876 extern __sfr __at 0xFB6 ECCP1AS;
883 unsigned ECCPASE : 1;
886 extern volatile __ECCP1AS_t __at 0xFB6 ECCP1ASbits;
888 extern __sfr __at 0xFB7 ECCP1DEL;
901 extern volatile __ECCP1DEL_t __at 0xFB7 ECCP1DELbits;
903 extern __sfr __at 0xFB8 BAUDCON;
916 extern volatile __BAUDCON_t __at 0xFB8 BAUDCONbits;
918 extern __sfr __at 0xFBA CCP2CON;
927 extern volatile __CCP2CON_t __at 0xFBA CCP2CONbits;
929 extern __sfr __at 0xFBB CCPR2L;
931 extern __sfr __at 0xFBC CCPR2H;
933 extern __sfr __at 0xFBD CCP1CON;
942 extern volatile __CCP1CON_t __at 0xFBD CCP1CONbits;
944 extern __sfr __at 0xFBE CCPR1L;
946 extern __sfr __at 0xFBF CCPR1H;
948 extern __sfr __at 0xFC0 ADCON2;
957 extern volatile __ADCON2_t __at 0xFC0 ADCON2bits;
959 extern __sfr __at 0xFC1 ADCON1;
968 extern volatile __ADCON1_t __at 0xFC1 ADCON1bits;
970 extern __sfr __at 0xFC2 ADCON0;
974 unsigned GO_nDONE : 1;
980 extern volatile __ADCON0_t __at 0xFC2 ADCON0bits;
982 extern __sfr __at 0xFC3 ADRESL;
984 extern __sfr __at 0xFC4 ADRESH;
986 extern __sfr __at 0xFC5 SSPCON2;
995 unsigned ACKSTAT : 1;
999 extern volatile __SSPCON2_t __at 0xFC5 SSPCON2bits;
1001 extern __sfr __at 0xFC6 SSPCON1;
1011 extern volatile __SSPCON1_t __at 0xFC6 SSPCON1bits;
1013 extern __sfr __at 0xFC7 SSPSTAT;
1026 extern volatile __SSPSTAT_t __at 0xFC7 SSPSTATbits;
1028 extern __sfr __at 0xFC8 SSPADD;
1030 extern __sfr __at 0xFC9 SSPBUF;
1032 extern __sfr __at 0xFCA T2CON;
1035 unsigned T2CKPS : 2;
1036 unsigned TMR2ON : 1;
1037 unsigned TOUTPS : 4;
1041 extern volatile __T2CON_t __at 0xFCA T2CONbits;
1043 extern __sfr __at 0xFCB PR2;
1045 extern __sfr __at 0xFCC TMR2;
1047 extern __sfr __at 0xFCD T1CON;
1050 unsigned TMR1ON : 1;
1051 unsigned TMR1CS : 1;
1052 unsigned nT1SYNC : 1;
1053 unsigned T1OSCEN : 1;
1054 unsigned T1CKPS : 2;
1059 extern volatile __T1CON_t __at 0xFCD T1CONbits;
1061 extern __sfr __at 0xFCE TMR1L;
1063 extern __sfr __at 0xFCF TMR1H;
1065 extern __sfr __at 0xFD0 RCON;
1074 unsigned SBOREN : 1;
1078 extern volatile __RCON_t __at 0xFD0 RCONbits;
1080 extern __sfr __at 0xFD1 WDTCON;
1083 unsigned SWDTEN : 1;
1093 extern volatile __WDTCON_t __at 0xFD1 WDTCONbits;
1095 extern __sfr __at 0xFD2 HLVDCON;
1099 unsigned HLVDEN : 1;
1102 unsigned VDIRMAG : 1;
1105 extern volatile __HLVDCON_t __at 0xFD2 HLVDCONbits;
1107 extern __sfr __at 0xFD3 OSCCON;
1117 extern volatile __OSCCON_t __at 0xFD3 OSCCONbits;
1119 extern __sfr __at 0xFD5 T0CON;
1126 unsigned T08BIT : 1;
1127 unsigned TMR0ON : 1;
1130 extern volatile __T0CON_t __at 0xFD5 T0CONbits;
1132 extern __sfr __at 0xFD6 TMR0L;
1134 extern __sfr __at 0xFD7 TMR0H;
1136 extern __sfr __at 0xFD8 STATUS;
1149 extern volatile __STATUS_t __at 0xFD8 STATUSbits;
1151 extern __sfr __at 0xFD9 FSR2L;
1153 extern __sfr __at 0xFDA FSR2H;
1163 extern volatile __FSR2H_t __at 0xFDA FSR2Hbits;
1165 extern __sfr __at 0xFDB PLUSW2;
1167 extern __sfr __at 0xFDC PREINC2;
1169 extern __sfr __at 0xFDD POSTDEC2;
1171 extern __sfr __at 0xFDE POSTINC2;
1173 extern __sfr __at 0xFDF INDF2;
1175 extern __sfr __at 0xFE0 BSR;
1185 extern volatile __BSR_t __at 0xFE0 BSRbits;
1187 extern __sfr __at 0xFE1 FSR1L;
1189 extern __sfr __at 0xFE2 FSR1H;
1199 extern volatile __FSR1H_t __at 0xFE2 FSR1Hbits;
1201 extern __sfr __at 0xFE3 PLUSW1;
1203 extern __sfr __at 0xFE4 PREINC1;
1205 extern __sfr __at 0xFE5 POSTDEC1;
1207 extern __sfr __at 0xFE6 POSTINC1;
1209 extern __sfr __at 0xFE7 INDF1;
1211 extern __sfr __at 0xFE8 WREG;
1213 extern __sfr __at 0xFE9 FSR0L;
1215 extern __sfr __at 0xFEA FSR0H;
1225 extern volatile __FSR0H_t __at 0xFEA FSR0Hbits;
1227 extern __sfr __at 0xFEB PLUSW0;
1229 extern __sfr __at 0xFEC PREINC0;
1231 extern __sfr __at 0xFED POSTDEC0;
1233 extern __sfr __at 0xFEE POSTINC0;
1235 extern __sfr __at 0xFEF INDF0;
1237 extern __sfr __at 0xFF0 INTCON3;
1240 unsigned INT1IF : 1;
1241 unsigned INT2IF : 1;
1243 unsigned INT1IE : 1;
1244 unsigned INT2IE : 1;
1246 unsigned INT1IP : 1;
1247 unsigned INT2IP : 1;
1250 extern volatile __INTCON3_t __at 0xFF0 INTCON3bits;
1252 extern __sfr __at 0xFF1 INTCON2;
1257 unsigned TMR0IP : 1;
1259 unsigned INTEDG2 : 1;
1260 unsigned INTEDG1 : 1;
1261 unsigned INTEDG0 : 1;
1265 extern volatile __INTCON2_t __at 0xFF1 INTCON2bits;
1267 extern __sfr __at 0xFF2 INTCON;
1271 unsigned INT0IF : 1;
1272 unsigned TMR0IF : 1;
1274 unsigned INT0IE : 1;
1275 unsigned TMR0IE : 1;
1276 unsigned PEIE_GIEL : 1;
1277 unsigned GIE_GIEH : 1;
1300 extern volatile __INTCON_t __at 0xFF2 INTCONbits;
1302 extern __sfr __at 0xFF3 PRODL;
1304 extern __sfr __at 0xFF4 PRODH;
1306 extern __sfr __at 0xFF5 TABLAT;
1308 extern __sfr __at 0xFF6 TBLPTRL;
1310 extern __sfr __at 0xFF7 TBLPTRH;
1312 extern __sfr __at 0xFF8 TBLPTRU;
1315 unsigned TBLPTRU : 5;
1321 extern volatile __TBLPTRU_t __at 0xFF8 TBLPTRUbits;
1323 extern __sfr __at 0xFF9 PCL;
1325 extern __sfr __at 0xFFA PCLATH;
1331 extern volatile __PCLATH_t __at 0xFFA PCLATHbits;
1333 extern __sfr __at 0xFFB PCLATU;
1342 extern volatile __PCLATU_t __at 0xFFB PCLATUbits;
1344 extern __sfr __at 0xFFC STKPTR;
1347 unsigned STKPTR : 5;
1349 unsigned STKUNF : 1;
1350 unsigned STKFUL : 1;
1353 extern volatile __STKPTR_t __at 0xFFC STKPTRbits;
1355 extern __sfr __at 0xFFD TOSL;
1357 extern __sfr __at 0xFFE TOSH;
1359 extern __sfr __at 0xFFF TOSU;
1368 extern volatile __TOSU_t __at 0xFFF TOSUbits;
1370 /* Configuration register locations */
1371 #define CONFIG1L 0x300000
1372 #define CONFIG1H 0x300001
1373 #define CONFIG2L 0x300002
1374 #define CONFIG2H 0x300003
1375 #define CONFIG3H 0x300005
1376 #define CONFIG4L 0x300006
1377 #define CONFIG5L 0x300008
1378 #define CONFIG5H 0x300009
1379 #define CONFIG6L 0x30000A
1380 #define CONFIG6H 0x30000B
1381 #define CONFIG7L 0x30000C
1382 #define CONFIG7H 0x30000D
1385 /* Full-Speed USB Clock Source Selection 1L options */
1386 #define _USBPLL_CLOCK_SRC_FROM_96MHZ_PLL_2_1L 0xFF /* Clock src from 96MHz PLL/2 */
1387 #define _USBPLL_CLOCK_SRC_FROM_OSC1_OSC2_1L 0xDF /* Clock src from OSC1/OSC2 */
1389 /* CPU System Clock Postscaler 1L options */
1390 #define _CPUDIV__OSC1_OSC2_SRC___4__96MHZ_PLL_SRC___6__1L 0xFF /* [OSC1/OSC2 Src: /4][96MHz PLL Src: /6] */
1391 #define _CPUDIV__OSC1_OSC2_SRC___3__96MHZ_PLL_SRC___4__1L 0xF7 /* [OSC1/OSC2 Src: /3][96MHz PLL Src: /4] */
1392 #define _CPUDIV__OSC1_OSC2_SRC___2__96MHZ_PLL_SRC___3__1L 0xEF /* [OSC1/OSC2 Src: /2][96MHz PLL Src: /3] */
1393 #define _CPUDIV__OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2__1L 0xE7 /* [OSC1/OSC2 Src: /1][96MHz PLL Src: /2] */
1395 /* 96MHz PLL Prescaler 1L options */
1396 #define _PLLDIV_DIVIDE_BY_12__48MHZ_INPUT__1L 0xFF /* Divide by 12 (48MHz input) */
1397 #define _PLLDIV_DIVIDE_BY_10__40MHZ_INPUT__1L 0xFE /* Divide by 10 (40MHz input) */
1398 #define _PLLDIV_DIVIDE_BY_6__24MHZ_INPUT__1L 0xFD /* Divide by 6 (24MHz input) */
1399 #define _PLLDIV_DIVIDE_BY_5__20MHZ_INPUT__1L 0xFC /* Divide by 5 (20MHz input) */
1400 #define _PLLDIV_DIVIDE_BY_4__16MHZ_INPUT__1L 0xFB /* Divide by 4 (16MHz input) */
1401 #define _PLLDIV_DIVIDE_BY_3__12MHZ_INPUT__1L 0xFA /* Divide by 3 (12MHz input) */
1402 #define _PLLDIV_DIVIDE_BY_2__8MHZ_INPUT__1L 0xF9 /* Divide by 2 (8MHz input) */
1403 #define _PLLDIV_NO_DIVIDE__4MHZ_INPUT__1L 0xF8 /* No Divide (4MHz input) */
1406 /* Oscillator 1H options */
1407 #define _OSC_HS__HS_PLL__USB_HS_1H 0xFE /* HS: HS+PLL, USB-HS */
1408 #define _OSC_HS__USB_HS_1H 0xFC /* HS: USB-HS */
1409 #define _OSC_INTOSC__USB_HS_1H 0xFB /* INTOSC: USB-HS */
1410 #define _OSC_INTOSC__USB_XT_1H 0xFA /* INTOSC: USB-XT */
1411 #define _OSC_INTOSC__INTOSC_CLK0_RA6___USB_EC_1H 0xF9 /* INTOSC: INTOSC+CLK0{RA6}, USB-EC */
1412 #define _OSC_INTOSC__INTOSC_RA6__USB_EC_1H 0xF8 /* INTOSC: INTOSC+RA6, USB-EC */
1413 #define _OSC_EC__EC_PLL__EC_PLL_CLKO_RA6___USB_EC_1H 0xF7 /* EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC */
1414 #define _OSC_EC__EC_PLL__EC_PLL_RA6__USB_EC_1H 0xF6 /* EC: EC+PLL, EC+PLL+RA6, USB-EC */
1415 #define _OSC_EC__EC_CLKO_RA6___USB_EC_1H 0xF5 /* EC: EC+CLKO{RA6}, USB-EC */
1416 #define _OSC_EC__EC_RA6__USB_EC_1H 0xF4 /* EC: EC+RA6, USB-EC */
1417 #define _OSC_XT__XT_PLL__USB_XT_1H 0xF2 /* XT: XT+PLL, USB-XT */
1418 #define _OSC_XT__USB_XT_1H 0xF0 /* XT: USB-XT */
1420 /* Fail-Safe Clock Monitor Enable 1H options */
1421 #define _FCMEN_OFF_1H 0xBF /* Disabled */
1422 #define _FCMEN_ON_1H 0xFF /* Enabled */
1424 /* Internal External Switch Over Mode 1H options */
1425 #define _IESO_OFF_1H 0x7F /* Disabled */
1426 #define _IESO_ON_1H 0xFF /* Enabled */
1429 /* USB Voltage Regulator 2L options */
1430 #define _VREGEN_ON_2L 0xFF /* Enabled */
1431 #define _VREGEN_OFF_2L 0xDF /* Disabled */
1433 /* Power Up Timer 2L options */
1434 #define _PUT_OFF_2L 0xFF /* Disabled */
1435 #define _PUT_ON_2L 0xFE /* Enabled */
1437 /* Brown Out Detect 2L options */
1438 #define _BODEN_ON_2L 0xFF /* Enabled in hardware, SBOREN disabled */
1439 #define _BODEN_ON_WHILE_ACTIVE_2L 0xFD /* Enabled while active,disabled in SLEEP,SBOREN disabled */
1440 #define _BODEN_CONTROLLED_WITH_SBOREN_BIT_2L 0xFB /* Controlled with SBOREN bit */
1441 #define _BODEN_OFF_2L 0xF9 /* Disabled in hardware, SBOREN disabled */
1443 /* Brown Out Voltage 2L options */
1444 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
1445 #define _BODENV_2_7V_2L 0xF7 /* 2.7V */
1446 #define _BODENV_4_2V_2L 0xEF /* 4.2V */
1447 #define _BODENV_4_5V_2L 0xE7 /* 4.5V */
1450 /* Watchdog Timer 2H options */
1451 #define _WDT_ON_2H 0xFF /* Enabled */
1452 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1454 /* Watchdog Postscaler 2H options */
1455 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1456 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1457 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1458 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1459 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1460 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1461 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1462 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1463 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1464 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1465 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1466 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1467 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1468 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1469 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1470 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1473 /* CCP2 Mux 3H options */
1474 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1475 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1477 /* PortB A/D Enable 3H options */
1478 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET_3H 0xFF /* PORTB<4:0> configured as analog inputs on RESET */
1479 #define _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H 0xFD /* PORTB<4:0> configured as digital I/O on RESET */
1481 /* Low Power Timer1 Osc enable 3H options */
1482 #define _LPT1OSC_ON_3H 0xFF /* Enabled */
1483 #define _LPT1OSC_OFF_3H 0xFB /* Disabled */
1485 /* Master Clear Enable 3H options */
1486 #define _MCLRE_MCLR_ON_RE3_OFF_3H 0xFF /* MCLR Enabled,RE3 Disabled */
1487 #define _MCLRE_MCLR_OFF_RE3_ON_3H 0x7F /* MCLR Disabled,RE3 Enabled */
1490 /* Stack Overflow Reset 4L options */
1491 #define _STVR_ON_4L 0xFF /* Enabled */
1492 #define _STVR_OFF_4L 0xFE /* Disabled */
1494 /* Low Voltage Program 4L options */
1495 #define _LVP_ON_4L 0xFF /* Enabled */
1496 #define _LVP_OFF_4L 0xFB /* Disabled */
1498 /* Dedicated In-Circuit Port {ICD/ICSP} 4L options */
1499 #define _ENICPORT_OFF_4L 0xDF /* Disabled */
1501 /* Extended CPU Enable 4L options */
1502 #define _ENHCPU_ON_4L 0xFF /* Enabled */
1503 #define _ENHCPU_OFF_4L 0xBF /* Disabled */
1505 /* Background Debug 4L options */
1506 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1507 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1510 /* Code Protect 00800-01FFF 5L options */
1511 #define _CP_0_OFF_5L 0xFF /* Disabled */
1512 #define _CP_0_ON_5L 0xFE /* Enabled */
1514 /* Code Protect 02000-03FFF 5L options */
1515 #define _CP_1_OFF_5L 0xFF /* Disabled */
1516 #define _CP_1_ON_5L 0xFD /* Enabled */
1518 /* Code Protect 04000-05FFF 5L options */
1519 #define _CP_2_OFF_5L 0xFF /* Disabled */
1520 #define _CP_2_ON_5L 0xFB /* Enabled */
1522 /* Code Protect 06000-07FFF 5L options */
1523 #define _CP_3_OFF_5L 0xFF /* Disabled */
1524 #define _CP_3_ON_5L 0xF7 /* Enabled */
1527 /* Data EE Read Protect 5H options */
1528 #define _CPD_OFF_5H 0xFF /* Disabled */
1529 #define _CPD_ON_5H 0x7F /* Enabled */
1531 /* Code Protect Boot 5H options */
1532 #define _CPB_OFF_5H 0xFF /* Disabled */
1533 #define _CPB_ON_5H 0xBF /* Enabled */
1536 /* Table Write Protect 00800-01FFF 6L options */
1537 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1538 #define _WRT_0_ON_6L 0xFE /* Enabled */
1540 /* Table Write Protect 02000-03FFF 6L options */
1541 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1542 #define _WRT_1_ON_6L 0xFD /* Enabled */
1544 /* Table Write Protect 04000-05FFF 6L options */
1545 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1546 #define _WRT_2_ON_6L 0xFB /* Enabled */
1548 /* Table Write Protect 06000-07FFF 6L options */
1549 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1550 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1553 /* Data EE Write Protect 6H options */
1554 #define _WRTD_OFF_6H 0xFF /* Disabled */
1555 #define _WRTD_ON_6H 0x7F /* Enabled */
1557 /* Table Write Protect Boot 6H options */
1558 #define _WRTB_OFF_6H 0xFF /* Disabled */
1559 #define _WRTB_ON_6H 0xBF /* Enabled */
1561 /* Config. Write Protect 6H options */
1562 #define _WRTC_OFF_6H 0xFF /* Disabled */
1563 #define _WRTC_ON_6H 0xDF /* Enabled */
1566 /* Table Read Protect 00800-01FFF 7L options */
1567 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1568 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1570 /* Table Read Protect 02000-03FFF 7L options */
1571 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1572 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1574 /* Table Read Protect 04000-05FFF 7L options */
1575 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1576 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1578 /* Table Read Protect 06000-07FFF 7L options */
1579 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1580 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1583 /* Table Read Protect Boot 7H options */
1584 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1585 #define _EBTRB_ON_7H 0xBF /* Enabled */
1589 /* Location of User ID words */
1590 #define __IDLOC0 0x200000
1591 #define __IDLOC1 0x200001
1592 #define __IDLOC2 0x200002
1593 #define __IDLOC3 0x200003
1594 #define __IDLOC4 0x200004
1595 #define __IDLOC5 0x200005
1596 #define __IDLOC6 0x200006
1597 #define __IDLOC7 0x200007
1599 #endif // __PIC18F2550__