2 // Register Declarations for Microchip 16F913 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTE_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define PIR1_ADDR 0x000C
40 #define PIR2_ADDR 0x000D
41 #define TMR1L_ADDR 0x000E
42 #define TMR1H_ADDR 0x000F
43 #define T1CON_ADDR 0x0010
44 #define TMR2_ADDR 0x0011
45 #define T2CON_ADDR 0x0012
46 #define SSPBUF_ADDR 0x0013
47 #define SSPCON_ADDR 0x0014
48 #define CCPR1L_ADDR 0x0015
49 #define CCPR1H_ADDR 0x0016
50 #define CCP1CON_ADDR 0x0017
51 #define RCSTA_ADDR 0x0018
52 #define TXREG_ADDR 0x0019
53 #define RCREG_ADDR 0x001A
54 #define ADRESH_ADDR 0x001E
55 #define ADCON0_ADDR 0x001F
56 #define OPTION_REG_ADDR 0x0081
57 #define TRISA_ADDR 0x0085
58 #define TRISB_ADDR 0x0086
59 #define TRISC_ADDR 0x0087
60 #define TRISE_ADDR 0x0089
61 #define PIE1_ADDR 0x008C
62 #define PIE2_ADDR 0x008D
63 #define PCON_ADDR 0x008E
64 #define OSCCON_ADDR 0x008F
65 #define OSCTUNE_ADDR 0x0090
66 #define ANSEL_ADDR 0x0091
67 #define PR2_ADDR 0x0092
68 #define SSPADD_ADDR 0x0093
69 #define SSPSTAT_ADDR 0x0094
70 #define WPUB_ADDR 0x0095
71 #define WPU_ADDR 0x0095
72 #define IOCB_ADDR 0x0096
73 #define IOC_ADDR 0x0096
74 #define CMCON1_ADDR 0x0097
75 #define TXSTA_ADDR 0x0098
76 #define SPBRG_ADDR 0x0099
77 #define CMCON0_ADDR 0x009C
78 #define VRCON_ADDR 0x009D
79 #define ADRESL_ADDR 0x009E
80 #define ADCON1_ADDR 0x009F
81 #define WDTCON_ADDR 0x0105
82 #define LCDCON_ADDR 0x0107
83 #define LCDPS_ADDR 0x0108
84 #define LVDCON_ADDR 0x0109
85 #define EEDATL_ADDR 0x010C
86 #define EEADRL_ADDR 0x010D
87 #define EEDATH_ADDR 0x010E
88 #define EEADRH_ADDR 0x010F
89 #define LCDDATA0_ADDR 0x0110
90 #define LCDDATA1_ADDR 0x0111
91 #define LCDDATA3_ADDR 0x0113
92 #define LCDDATA4_ADDR 0x0114
93 #define LCDDATA6_ADDR 0x0116
94 #define LCDDATA7_ADDR 0x0117
95 #define LCDDATA9_ADDR 0x0119
96 #define LCDDATA10_ADDR 0x011A
97 #define LCDSE0_ADDR 0x011C
98 #define LCDSE1_ADDR 0x011D
99 #define EECON1_ADDR 0x018C
100 #define EECON2_ADDR 0x018D
103 // Memory organization.
109 // P16F913.INC Standard Header File, Version 1.04 Microchip Technology, Inc.
112 // This header file defines configurations, registers, and other useful bits of
113 // information for the PIC16F913 microcontroller.
114 // These names are taken to match the data sheets as closely as possible.
116 // Note that the processor must be selected before this file is
117 // included. The processor may be selected the following ways:
119 // 1. Command line switch:
120 // C:\ MPASM MYFILE.ASM /PIC16F913
121 // 2. LIST directive in the source file
123 // 3. Processor Type entry in the MPASM full-screen interface
125 //==========================================================================
129 //==========================================================================
132 //1.00 06/11/04 Initial Release
133 //1.01 06/18/04 Corrected typo in 'bad ram' section
134 //1.02 08/16/04 Added EECON2
135 //1.03 05/20/05 Removed EECON2 from badram
136 //1.04 10/05/05 Correct names of bits in ANSEL, Add EEADRH and EEADRL bit
140 //==========================================================================
144 //==========================================================================
147 // MESSG "Processor-header file mismatch. Verify selected processor."
150 //==========================================================================
152 // Register Definitions
154 //==========================================================================
159 //----- Register Files------------------------------------------------------
161 extern __sfr __at (INDF_ADDR) INDF;
162 extern __sfr __at (TMR0_ADDR) TMR0;
163 extern __sfr __at (PCL_ADDR) PCL;
164 extern __sfr __at (STATUS_ADDR) STATUS;
165 extern __sfr __at (FSR_ADDR) FSR;
166 extern __sfr __at (PORTA_ADDR) PORTA;
167 extern __sfr __at (PORTB_ADDR) PORTB;
168 extern __sfr __at (PORTC_ADDR) PORTC;
169 extern __sfr __at (PORTE_ADDR) PORTE;
170 extern __sfr __at (PCLATH_ADDR) PCLATH;
171 extern __sfr __at (INTCON_ADDR) INTCON;
172 extern __sfr __at (PIR1_ADDR) PIR1;
173 extern __sfr __at (PIR2_ADDR) PIR2;
174 extern __sfr __at (TMR1L_ADDR) TMR1L;
175 extern __sfr __at (TMR1H_ADDR) TMR1H;
176 extern __sfr __at (T1CON_ADDR) T1CON;
177 extern __sfr __at (TMR2_ADDR) TMR2;
178 extern __sfr __at (T2CON_ADDR) T2CON;
179 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
180 extern __sfr __at (SSPCON_ADDR) SSPCON;
181 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
182 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
183 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
184 extern __sfr __at (RCSTA_ADDR) RCSTA;
185 extern __sfr __at (TXREG_ADDR) TXREG;
186 extern __sfr __at (RCREG_ADDR) RCREG;
187 extern __sfr __at (ADRESH_ADDR) ADRESH;
188 extern __sfr __at (ADCON0_ADDR) ADCON0;
190 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
191 extern __sfr __at (TRISA_ADDR) TRISA;
192 extern __sfr __at (TRISB_ADDR) TRISB;
193 extern __sfr __at (TRISC_ADDR) TRISC;
194 extern __sfr __at (TRISE_ADDR) TRISE;
195 extern __sfr __at (PIE1_ADDR) PIE1;
196 extern __sfr __at (PIE2_ADDR) PIE2;
197 extern __sfr __at (PCON_ADDR) PCON;
198 extern __sfr __at (OSCCON_ADDR) OSCCON;
199 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
200 extern __sfr __at (ANSEL_ADDR) ANSEL;
201 extern __sfr __at (PR2_ADDR) PR2;
202 extern __sfr __at (SSPADD_ADDR) SSPADD;
203 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
204 extern __sfr __at (WPUB_ADDR) WPUB;
205 extern __sfr __at (WPU_ADDR) WPU;
206 extern __sfr __at (IOCB_ADDR) IOCB;
207 extern __sfr __at (IOC_ADDR) IOC;
208 extern __sfr __at (CMCON1_ADDR) CMCON1;
209 extern __sfr __at (TXSTA_ADDR) TXSTA;
210 extern __sfr __at (SPBRG_ADDR) SPBRG;
211 extern __sfr __at (CMCON0_ADDR) CMCON0;
212 extern __sfr __at (VRCON_ADDR) VRCON;
213 extern __sfr __at (ADRESL_ADDR) ADRESL;
214 extern __sfr __at (ADCON1_ADDR) ADCON1;
216 extern __sfr __at (WDTCON_ADDR) WDTCON;
217 extern __sfr __at (LCDCON_ADDR) LCDCON;
218 extern __sfr __at (LCDPS_ADDR) LCDPS;
219 extern __sfr __at (LVDCON_ADDR) LVDCON;
220 extern __sfr __at (EEDATL_ADDR) EEDATL;
221 extern __sfr __at (EEADRL_ADDR) EEADRL;
222 extern __sfr __at (EEDATH_ADDR) EEDATH;
223 extern __sfr __at (EEADRH_ADDR) EEADRH;
224 extern __sfr __at (LCDDATA0_ADDR) LCDDATA0;
225 extern __sfr __at (LCDDATA1_ADDR) LCDDATA1;
226 extern __sfr __at (LCDDATA3_ADDR) LCDDATA3;
227 extern __sfr __at (LCDDATA4_ADDR) LCDDATA4;
228 extern __sfr __at (LCDDATA6_ADDR) LCDDATA6;
229 extern __sfr __at (LCDDATA7_ADDR) LCDDATA7;
230 extern __sfr __at (LCDDATA9_ADDR) LCDDATA9;
231 extern __sfr __at (LCDDATA10_ADDR) LCDDATA10;
232 extern __sfr __at (LCDSE0_ADDR) LCDSE0;
233 extern __sfr __at (LCDSE1_ADDR) LCDSE1;
235 extern __sfr __at (EECON1_ADDR) EECON1;
236 extern __sfr __at (EECON2_ADDR) EECON2;
238 //----- STATUS Bits --------------------------------------------------------
241 //----- INTCON Bits --------------------------------------------------------
244 //----- PIR1 Bits ----------------------------------------------------------
247 //----- PIR2 Bits ----------------------------------------------------------
250 //----- T1CON Bits ---------------------------------------------------------
253 //----- T2CON Bits ---------------------------------------------------------
256 //----- SSPCON Bits --------------------------------------------------------
259 //----- CCP1CON Bits -------------------------------------------------------
262 //----- RCSTA Bits ---------------------------------------------------------
266 //----- ADCON0 Bits --------------------------------------------------------
269 //----- OPTION_REG Bits -----------------------------------------------------
272 //----- PIE1 Bits ----------------------------------------------------------
275 //----- PIE2 Bits ----------------------------------------------------------
278 //----- PCON Bits ----------------------------------------------------------
281 //----- OSCCON Bits -------------------------------------------------------
284 //----- OSCTUNE Bits -------------------------------------------------------
288 //----- ANSEL Bits ---------------------------------------------------------
292 //----- SSPSTAT Bits -------------------------------------------------------
296 //----- WPUB Bits -------------------------------------------------------
299 //----- WPU Bits -------------------------------------------------------
303 //----- IOCB Bits -------------------------------------------------------
307 //----- IOC Bits -------------------------------------------------------
311 //----- CMCON1 Bits --------------------------------------------------------
314 //----- TXSTA Bits ---------------------------------------------------------
318 //----- CMCON0 Bits ---------------------------------------------------------
321 //----- VRCON Bits --------------------------------------------------------
324 //----- ADCON1 Bits --------------------------------------------------------
327 //----- WDTCON Bits --------------------------------------------------------
330 //----- LCDCON Bits --------------------------------------------------------
333 //----- LCDPS Bits ---------------------------------------------------------
336 //----- LVDCON Bits --------------------------------------------------------
339 //----- LCDDATA0 Bits -------------------------------------------------------
343 //----- LCDDATA1 Bits -------------------------------------------------------
348 //----- LCDDATA3 Bits -------------------------------------------------------
352 //----- LCDDATA4 Bits -------------------------------------------------------
357 //----- LCDDATA6 Bits -------------------------------------------------------
361 //----- LCDDATA7 Bits -------------------------------------------------------
366 //----- LCDDATA9 Bits -------------------------------------------------------
370 //----- LCDDATA10 Bits -------------------------------------------------------
375 //----- LCDSE0 Bits --------------------------------------------------------
379 //----- LCDSE1 Bits --------------------------------------------------------
384 //----- EECON1 Bits --------------------------------------------------------
387 //----- EEADRH Bits --------------------------------------------------------
390 //----- EEADRL Bits --------------------------------------------------------
394 //==========================================================================
398 //==========================================================================
401 // __BADRAM H'08', H'1B'-H'1D'
402 // __BADRAM H'88', H'9A'-H'9B'
403 // __BADRAM H'112', H'115', H'118', H'11B',H'11E'-H'11F'
404 // __BADRAM H'185', H'187'-H'189', H'18E'-H'1EF'
406 //==========================================================================
408 // Configuration Bits
410 //==========================================================================
412 #define _CONFIG 0x2007
414 //Configuration Byte 1 Options
415 #define _DEBUG_ON 0x2FFF
416 #define _DEBUG_OFF 0x3FFF
417 #define _FCMEN_ON 0x3FFF
418 #define _FCMEN_OFF 0x37FF
419 #define _IESO_ON 0x3FFF
420 #define _IESO_OFF 0x3BFF
421 #define _BOD_ON 0x3FFF
422 #define _BOD_NSLEEP 0x3EFF
423 #define _BOD_SBODEN 0x3DFF
424 #define _BOD_OFF 0x3CFF
425 #define _CPD_ON 0x3F7F
426 #define _CPD_OFF 0x3FFF
427 #define _CP_ON 0x3FBF
428 #define _CP_OFF 0x3FFF
429 #define _MCLRE_ON 0x3FFF
430 #define _MCLRE_OFF 0x3FDF
431 #define _PWRTE_ON 0x3FEF
432 #define _PWRTE_OFF 0x3FFF
433 #define _WDT_ON 0x3FFF
434 #define _WDT_OFF 0x3FF7
435 #define _LP_OSC 0x3FF8
436 #define _XT_OSC 0x3FF9
437 #define _HS_OSC 0x3FFA
438 #define _EC_OSC 0x3FFB
439 #define _INTRC_OSC_NOCLKOUT 0x3FFC
440 #define _INTRC_OSC_CLKOUT 0x3FFD
441 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
442 #define _EXTRC_OSC_CLKOUT 0x3FFF
443 #define _INTOSCIO 0x3FFC
444 #define _INTOSC 0x3FFD
445 #define _EXTRCIO 0x3FFE
446 #define _EXTRC 0x3FFF
451 // ----- ADCON0 bits --------------------
454 unsigned char ADON:1;
455 unsigned char NOT_DONE:1;
456 unsigned char CHS0:1;
457 unsigned char CHS1:1;
458 unsigned char CHS2:1;
459 unsigned char VCFG0:1;
460 unsigned char VCFG1:1;
461 unsigned char ADFM:1;
465 unsigned char GO_DONE:1;
474 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
476 #define ADON ADCON0_bits.ADON
477 #define NOT_DONE ADCON0_bits.NOT_DONE
478 #define GO_DONE ADCON0_bits.GO_DONE
479 #define CHS0 ADCON0_bits.CHS0
480 #define CHS1 ADCON0_bits.CHS1
481 #define CHS2 ADCON0_bits.CHS2
482 #define VCFG0 ADCON0_bits.VCFG0
483 #define VCFG1 ADCON0_bits.VCFG1
484 #define ADFM ADCON0_bits.ADFM
486 // ----- ADCON1 bits --------------------
493 unsigned char ADCS0:1;
494 unsigned char ADCS1:1;
495 unsigned char ADCS2:1;
499 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
501 #define ADCS0 ADCON1_bits.ADCS0
502 #define ADCS1 ADCON1_bits.ADCS1
503 #define ADCS2 ADCON1_bits.ADCS2
505 // ----- ANSEL bits --------------------
508 unsigned char ANS0:1;
509 unsigned char ANS1:1;
510 unsigned char ANS2:1;
511 unsigned char ANS3:1;
512 unsigned char ANS4:1;
528 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
530 #define ANS0 ANSEL_bits.ANS0
531 #define AN0 ANSEL_bits.AN0
532 #define ANS1 ANSEL_bits.ANS1
533 #define AN1 ANSEL_bits.AN1
534 #define ANS2 ANSEL_bits.ANS2
535 #define AN2 ANSEL_bits.AN2
536 #define ANS3 ANSEL_bits.ANS3
537 #define AN3 ANSEL_bits.AN3
538 #define ANS4 ANSEL_bits.ANS4
539 #define AN4 ANSEL_bits.AN4
541 // ----- CCP1CON bits --------------------
544 unsigned char CCP1M0:1;
545 unsigned char CCP1M1:1;
546 unsigned char CCP1M2:1;
547 unsigned char CCP1M3:1;
548 unsigned char CCP1Y:1;
549 unsigned char CCP1X:1;
554 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
556 #define CCP1M0 CCP1CON_bits.CCP1M0
557 #define CCP1M1 CCP1CON_bits.CCP1M1
558 #define CCP1M2 CCP1CON_bits.CCP1M2
559 #define CCP1M3 CCP1CON_bits.CCP1M3
560 #define CCP1Y CCP1CON_bits.CCP1Y
561 #define CCP1X CCP1CON_bits.CCP1X
563 // ----- CMCON0 bits --------------------
570 unsigned char C1INV:1;
571 unsigned char C2INV:1;
572 unsigned char C1OUT:1;
573 unsigned char C2OUT:1;
576 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
578 #define CM0 CMCON0_bits.CM0
579 #define CM1 CMCON0_bits.CM1
580 #define CM2 CMCON0_bits.CM2
581 #define CIS CMCON0_bits.CIS
582 #define C1INV CMCON0_bits.C1INV
583 #define C2INV CMCON0_bits.C2INV
584 #define C1OUT CMCON0_bits.C1OUT
585 #define C2OUT CMCON0_bits.C2OUT
587 // ----- CMCON1 bits --------------------
590 unsigned char C2SYNC:1;
591 unsigned char T1GSS:1;
600 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
602 #define C2SYNC CMCON1_bits.C2SYNC
603 #define T1GSS CMCON1_bits.T1GSS
605 // ----- EEADRH bits --------------------
608 unsigned char EEADRH0:1;
609 unsigned char EEADRH1:1;
610 unsigned char EEADRH2:1;
611 unsigned char EEADRH3:1;
612 unsigned char EEADRH4:1;
618 extern volatile __EEADRH_bits_t __at(EEADRH_ADDR) EEADRH_bits;
620 #define EEADRH0 EEADRH_bits.EEADRH0
621 #define EEADRH1 EEADRH_bits.EEADRH1
622 #define EEADRH2 EEADRH_bits.EEADRH2
623 #define EEADRH3 EEADRH_bits.EEADRH3
624 #define EEADRH4 EEADRH_bits.EEADRH4
626 // ----- EEADRL bits --------------------
629 unsigned char EEADRL0:1;
630 unsigned char EEADRL1:1;
631 unsigned char EEADRL2:1;
632 unsigned char EEADRL3:1;
633 unsigned char EEADRL4:1;
634 unsigned char EEADRL5:1;
635 unsigned char EEADRL6:1;
636 unsigned char EEADRL7:1;
639 extern volatile __EEADRL_bits_t __at(EEADRL_ADDR) EEADRL_bits;
641 #define EEADRL0 EEADRL_bits.EEADRL0
642 #define EEADRL1 EEADRL_bits.EEADRL1
643 #define EEADRL2 EEADRL_bits.EEADRL2
644 #define EEADRL3 EEADRL_bits.EEADRL3
645 #define EEADRL4 EEADRL_bits.EEADRL4
646 #define EEADRL5 EEADRL_bits.EEADRL5
647 #define EEADRL6 EEADRL_bits.EEADRL6
648 #define EEADRL7 EEADRL_bits.EEADRL7
650 // ----- EECON1 bits --------------------
655 unsigned char WREN:1;
656 unsigned char WRERR:1;
660 unsigned char EEPGD:1;
663 unsigned char EERD:1;
664 unsigned char EEWR:1;
673 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
675 #define RD EECON1_bits.RD
676 #define EERD EECON1_bits.EERD
677 #define WR EECON1_bits.WR
678 #define EEWR EECON1_bits.EEWR
679 #define WREN EECON1_bits.WREN
680 #define WRERR EECON1_bits.WRERR
681 #define EEPGD EECON1_bits.EEPGD
683 // ----- INTCON bits --------------------
686 unsigned char RBIF:1;
687 unsigned char INTF:1;
688 unsigned char T0IF:1;
689 unsigned char RBIE:1;
690 unsigned char INTE:1;
691 unsigned char T0IE:1;
692 unsigned char PEIE:1;
698 unsigned char TMR0IF:1;
701 unsigned char TMR0IE:1;
706 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
708 #define RBIF INTCON_bits.RBIF
709 #define INTF INTCON_bits.INTF
710 #define T0IF INTCON_bits.T0IF
711 #define TMR0IF INTCON_bits.TMR0IF
712 #define RBIE INTCON_bits.RBIE
713 #define INTE INTCON_bits.INTE
714 #define T0IE INTCON_bits.T0IE
715 #define TMR0IE INTCON_bits.TMR0IE
716 #define PEIE INTCON_bits.PEIE
717 #define GIE INTCON_bits.GIE
719 // ----- IOC bits --------------------
726 unsigned char IOC4:1;
727 unsigned char IOC5:1;
728 unsigned char IOC6:1;
729 unsigned char IOC7:1;
732 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
734 #define IOC4 IOC_bits.IOC4
735 #define IOC5 IOC_bits.IOC5
736 #define IOC6 IOC_bits.IOC6
737 #define IOC7 IOC_bits.IOC7
739 // ----- IOCB bits --------------------
746 unsigned char IOCB4:1;
747 unsigned char IOCB5:1;
748 unsigned char IOCB6:1;
749 unsigned char IOCB7:1;
752 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
754 #define IOCB4 IOCB_bits.IOCB4
755 #define IOCB5 IOCB_bits.IOCB5
756 #define IOCB6 IOCB_bits.IOCB6
757 #define IOCB7 IOCB_bits.IOCB7
759 // ----- LCDCON bits --------------------
762 unsigned char LMUX0:1;
763 unsigned char LMUX1:1;
766 unsigned char VLCDEN:1;
767 unsigned char WERR:1;
768 unsigned char SLPEN:1;
769 unsigned char LCDEN:1;
772 extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits;
774 #define LMUX0 LCDCON_bits.LMUX0
775 #define LMUX1 LCDCON_bits.LMUX1
776 #define CS0 LCDCON_bits.CS0
777 #define CS1 LCDCON_bits.CS1
778 #define VLCDEN LCDCON_bits.VLCDEN
779 #define WERR LCDCON_bits.WERR
780 #define SLPEN LCDCON_bits.SLPEN
781 #define LCDEN LCDCON_bits.LCDEN
783 // ----- LCDDATA0 bits --------------------
786 unsigned char SEG0COM0:1;
787 unsigned char SEG1COM0:1;
788 unsigned char SEG2COM0:1;
789 unsigned char SEG3COM0:1;
790 unsigned char SEG4COM0:1;
791 unsigned char SEG5COM0:1;
792 unsigned char SEG6COM0:1;
793 unsigned char SEG7COM0:1;
796 unsigned char S0C0:1;
797 unsigned char S1C0:1;
798 unsigned char S2C0:1;
799 unsigned char S3C0:1;
800 unsigned char S4C0:1;
801 unsigned char S5C0:1;
802 unsigned char S6C0:1;
803 unsigned char S7C0:1;
806 extern volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits;
808 #define SEG0COM0 LCDDATA0_bits.SEG0COM0
809 #define S0C0 LCDDATA0_bits.S0C0
810 #define SEG1COM0 LCDDATA0_bits.SEG1COM0
811 #define S1C0 LCDDATA0_bits.S1C0
812 #define SEG2COM0 LCDDATA0_bits.SEG2COM0
813 #define S2C0 LCDDATA0_bits.S2C0
814 #define SEG3COM0 LCDDATA0_bits.SEG3COM0
815 #define S3C0 LCDDATA0_bits.S3C0
816 #define SEG4COM0 LCDDATA0_bits.SEG4COM0
817 #define S4C0 LCDDATA0_bits.S4C0
818 #define SEG5COM0 LCDDATA0_bits.SEG5COM0
819 #define S5C0 LCDDATA0_bits.S5C0
820 #define SEG6COM0 LCDDATA0_bits.SEG6COM0
821 #define S6C0 LCDDATA0_bits.S6C0
822 #define SEG7COM0 LCDDATA0_bits.SEG7COM0
823 #define S7C0 LCDDATA0_bits.S7C0
825 // ----- LCDDATA1 bits --------------------
828 unsigned char SEG8COM0:1;
829 unsigned char SEG9COM0:1;
830 unsigned char SEG10COM0:1;
831 unsigned char SEG11COM0:1;
832 unsigned char SEG12COM0:1;
833 unsigned char SEG13COM0:1;
834 unsigned char SEG14COM0:1;
835 unsigned char SEG15COM0:1;
838 unsigned char S8C0:1;
839 unsigned char S9C0:1;
840 unsigned char S10C0:1;
841 unsigned char S11C0:1;
842 unsigned char S12C0:1;
843 unsigned char S13C0:1;
844 unsigned char S14C0:1;
845 unsigned char S15C0:1;
848 extern volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits;
850 #define SEG8COM0 LCDDATA1_bits.SEG8COM0
851 #define S8C0 LCDDATA1_bits.S8C0
852 #define SEG9COM0 LCDDATA1_bits.SEG9COM0
853 #define S9C0 LCDDATA1_bits.S9C0
854 #define SEG10COM0 LCDDATA1_bits.SEG10COM0
855 #define S10C0 LCDDATA1_bits.S10C0
856 #define SEG11COM0 LCDDATA1_bits.SEG11COM0
857 #define S11C0 LCDDATA1_bits.S11C0
858 #define SEG12COM0 LCDDATA1_bits.SEG12COM0
859 #define S12C0 LCDDATA1_bits.S12C0
860 #define SEG13COM0 LCDDATA1_bits.SEG13COM0
861 #define S13C0 LCDDATA1_bits.S13C0
862 #define SEG14COM0 LCDDATA1_bits.SEG14COM0
863 #define S14C0 LCDDATA1_bits.S14C0
864 #define SEG15COM0 LCDDATA1_bits.SEG15COM0
865 #define S15C0 LCDDATA1_bits.S15C0
867 // ----- LCDDATA10 bits --------------------
870 unsigned char SEG8COM3:1;
871 unsigned char SEG9COM3:1;
872 unsigned char SEG10COM3:1;
873 unsigned char SEG11COM3:1;
874 unsigned char SEG12COM3:1;
875 unsigned char SEG13COM3:1;
876 unsigned char SEG14COM3:1;
877 unsigned char SEG15COM3:1;
880 unsigned char S8C3:1;
881 unsigned char S9C3:1;
882 unsigned char S10C3:1;
883 unsigned char S11C3:1;
884 unsigned char S12C3:1;
885 unsigned char S13C3:1;
886 unsigned char S14C3:1;
887 unsigned char S15C3:1;
889 } __LCDDATA10_bits_t;
890 extern volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits;
892 #define SEG8COM3 LCDDATA10_bits.SEG8COM3
893 #define S8C3 LCDDATA10_bits.S8C3
894 #define SEG9COM3 LCDDATA10_bits.SEG9COM3
895 #define S9C3 LCDDATA10_bits.S9C3
896 #define SEG10COM3 LCDDATA10_bits.SEG10COM3
897 #define S10C3 LCDDATA10_bits.S10C3
898 #define SEG11COM3 LCDDATA10_bits.SEG11COM3
899 #define S11C3 LCDDATA10_bits.S11C3
900 #define SEG12COM3 LCDDATA10_bits.SEG12COM3
901 #define S12C3 LCDDATA10_bits.S12C3
902 #define SEG13COM3 LCDDATA10_bits.SEG13COM3
903 #define S13C3 LCDDATA10_bits.S13C3
904 #define SEG14COM3 LCDDATA10_bits.SEG14COM3
905 #define S14C3 LCDDATA10_bits.S14C3
906 #define SEG15COM3 LCDDATA10_bits.SEG15COM3
907 #define S15C3 LCDDATA10_bits.S15C3
909 // ----- LCDDATA3 bits --------------------
912 unsigned char SEG0COM1:1;
913 unsigned char SEG1COM1:1;
914 unsigned char SEG2COM1:1;
915 unsigned char SEG3COM1:1;
916 unsigned char SEG4COM1:1;
917 unsigned char SEG5COM1:1;
918 unsigned char SEG6COM1:1;
919 unsigned char SEG7COM1:1;
922 unsigned char S0C1:1;
923 unsigned char S1C1:1;
924 unsigned char S2C1:1;
925 unsigned char S3C1:1;
926 unsigned char S4C1:1;
927 unsigned char S5C1:1;
928 unsigned char S6C1:1;
929 unsigned char S7C1:1;
932 extern volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits;
934 #define SEG0COM1 LCDDATA3_bits.SEG0COM1
935 #define S0C1 LCDDATA3_bits.S0C1
936 #define SEG1COM1 LCDDATA3_bits.SEG1COM1
937 #define S1C1 LCDDATA3_bits.S1C1
938 #define SEG2COM1 LCDDATA3_bits.SEG2COM1
939 #define S2C1 LCDDATA3_bits.S2C1
940 #define SEG3COM1 LCDDATA3_bits.SEG3COM1
941 #define S3C1 LCDDATA3_bits.S3C1
942 #define SEG4COM1 LCDDATA3_bits.SEG4COM1
943 #define S4C1 LCDDATA3_bits.S4C1
944 #define SEG5COM1 LCDDATA3_bits.SEG5COM1
945 #define S5C1 LCDDATA3_bits.S5C1
946 #define SEG6COM1 LCDDATA3_bits.SEG6COM1
947 #define S6C1 LCDDATA3_bits.S6C1
948 #define SEG7COM1 LCDDATA3_bits.SEG7COM1
949 #define S7C1 LCDDATA3_bits.S7C1
951 // ----- LCDDATA4 bits --------------------
954 unsigned char SEG8COM1:1;
955 unsigned char SEG9COM1:1;
956 unsigned char SEG10COM1:1;
957 unsigned char SEG11COM1:1;
958 unsigned char SEG12COM1:1;
959 unsigned char SEG13COM1:1;
960 unsigned char SEG14COM1:1;
961 unsigned char SEG15COM1:1;
964 unsigned char S8C1:1;
965 unsigned char S9C1:1;
966 unsigned char S10C1:1;
967 unsigned char S11C1:1;
968 unsigned char S12C1:1;
969 unsigned char S13C1:1;
970 unsigned char S14C1:1;
971 unsigned char S15C1:1;
974 extern volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits;
976 #define SEG8COM1 LCDDATA4_bits.SEG8COM1
977 #define S8C1 LCDDATA4_bits.S8C1
978 #define SEG9COM1 LCDDATA4_bits.SEG9COM1
979 #define S9C1 LCDDATA4_bits.S9C1
980 #define SEG10COM1 LCDDATA4_bits.SEG10COM1
981 #define S10C1 LCDDATA4_bits.S10C1
982 #define SEG11COM1 LCDDATA4_bits.SEG11COM1
983 #define S11C1 LCDDATA4_bits.S11C1
984 #define SEG12COM1 LCDDATA4_bits.SEG12COM1
985 #define S12C1 LCDDATA4_bits.S12C1
986 #define SEG13COM1 LCDDATA4_bits.SEG13COM1
987 #define S13C1 LCDDATA4_bits.S13C1
988 #define SEG14COM1 LCDDATA4_bits.SEG14COM1
989 #define S14C1 LCDDATA4_bits.S14C1
990 #define SEG15COM1 LCDDATA4_bits.SEG15COM1
991 #define S15C1 LCDDATA4_bits.S15C1
993 // ----- LCDDATA6 bits --------------------
996 unsigned char SEG0COM2:1;
997 unsigned char SEG1COM2:1;
998 unsigned char SEG2COM2:1;
999 unsigned char SEG3COM2:1;
1000 unsigned char SEG4COM2:1;
1001 unsigned char SEG5COM2:1;
1002 unsigned char SEG6COM2:1;
1003 unsigned char SEG7COM2:1;
1006 unsigned char S0C2:1;
1007 unsigned char S1C2:1;
1008 unsigned char S2C2:1;
1009 unsigned char S3C2:1;
1010 unsigned char S4C2:1;
1011 unsigned char S5C2:1;
1012 unsigned char S6C2:1;
1013 unsigned char S7C2:1;
1015 } __LCDDATA6_bits_t;
1016 extern volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits;
1018 #define SEG0COM2 LCDDATA6_bits.SEG0COM2
1019 #define S0C2 LCDDATA6_bits.S0C2
1020 #define SEG1COM2 LCDDATA6_bits.SEG1COM2
1021 #define S1C2 LCDDATA6_bits.S1C2
1022 #define SEG2COM2 LCDDATA6_bits.SEG2COM2
1023 #define S2C2 LCDDATA6_bits.S2C2
1024 #define SEG3COM2 LCDDATA6_bits.SEG3COM2
1025 #define S3C2 LCDDATA6_bits.S3C2
1026 #define SEG4COM2 LCDDATA6_bits.SEG4COM2
1027 #define S4C2 LCDDATA6_bits.S4C2
1028 #define SEG5COM2 LCDDATA6_bits.SEG5COM2
1029 #define S5C2 LCDDATA6_bits.S5C2
1030 #define SEG6COM2 LCDDATA6_bits.SEG6COM2
1031 #define S6C2 LCDDATA6_bits.S6C2
1032 #define SEG7COM2 LCDDATA6_bits.SEG7COM2
1033 #define S7C2 LCDDATA6_bits.S7C2
1035 // ----- LCDDATA7 bits --------------------
1038 unsigned char SEG8COM2:1;
1039 unsigned char SEG9COM2:1;
1040 unsigned char SEG10COM2:1;
1041 unsigned char SEG11COM2:1;
1042 unsigned char SEG12COM2:1;
1043 unsigned char SEG13COM2:1;
1044 unsigned char SEG14COM2:1;
1045 unsigned char SEG15COM2:1;
1048 unsigned char S8C2:1;
1049 unsigned char S9C2:1;
1050 unsigned char S10C2:1;
1051 unsigned char S11C2:1;
1052 unsigned char S12C2:1;
1053 unsigned char S13C2:1;
1054 unsigned char S14C2:1;
1055 unsigned char S15C2:1;
1057 } __LCDDATA7_bits_t;
1058 extern volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits;
1060 #define SEG8COM2 LCDDATA7_bits.SEG8COM2
1061 #define S8C2 LCDDATA7_bits.S8C2
1062 #define SEG9COM2 LCDDATA7_bits.SEG9COM2
1063 #define S9C2 LCDDATA7_bits.S9C2
1064 #define SEG10COM2 LCDDATA7_bits.SEG10COM2
1065 #define S10C2 LCDDATA7_bits.S10C2
1066 #define SEG11COM2 LCDDATA7_bits.SEG11COM2
1067 #define S11C2 LCDDATA7_bits.S11C2
1068 #define SEG12COM2 LCDDATA7_bits.SEG12COM2
1069 #define S12C2 LCDDATA7_bits.S12C2
1070 #define SEG13COM2 LCDDATA7_bits.SEG13COM2
1071 #define S13C2 LCDDATA7_bits.S13C2
1072 #define SEG14COM2 LCDDATA7_bits.SEG14COM2
1073 #define S14C2 LCDDATA7_bits.S14C2
1074 #define SEG15COM2 LCDDATA7_bits.SEG15COM2
1075 #define S15C2 LCDDATA7_bits.S15C2
1077 // ----- LCDDATA9 bits --------------------
1080 unsigned char SEG0COM3:1;
1081 unsigned char SEG1COM3:1;
1082 unsigned char SEG2COM3:1;
1083 unsigned char SEG3COM3:1;
1084 unsigned char SEG4COM3:1;
1085 unsigned char SEG5COM3:1;
1086 unsigned char SEG6COM3:1;
1087 unsigned char SEG7COM3:1;
1090 unsigned char S0C3:1;
1091 unsigned char S1C3:1;
1092 unsigned char S2C3:1;
1093 unsigned char S3C3:1;
1094 unsigned char S4C3:1;
1095 unsigned char S5C3:1;
1096 unsigned char S6C3:1;
1097 unsigned char S7C3:1;
1099 } __LCDDATA9_bits_t;
1100 extern volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits;
1102 #define SEG0COM3 LCDDATA9_bits.SEG0COM3
1103 #define S0C3 LCDDATA9_bits.S0C3
1104 #define SEG1COM3 LCDDATA9_bits.SEG1COM3
1105 #define S1C3 LCDDATA9_bits.S1C3
1106 #define SEG2COM3 LCDDATA9_bits.SEG2COM3
1107 #define S2C3 LCDDATA9_bits.S2C3
1108 #define SEG3COM3 LCDDATA9_bits.SEG3COM3
1109 #define S3C3 LCDDATA9_bits.S3C3
1110 #define SEG4COM3 LCDDATA9_bits.SEG4COM3
1111 #define S4C3 LCDDATA9_bits.S4C3
1112 #define SEG5COM3 LCDDATA9_bits.SEG5COM3
1113 #define S5C3 LCDDATA9_bits.S5C3
1114 #define SEG6COM3 LCDDATA9_bits.SEG6COM3
1115 #define S6C3 LCDDATA9_bits.S6C3
1116 #define SEG7COM3 LCDDATA9_bits.SEG7COM3
1117 #define S7C3 LCDDATA9_bits.S7C3
1119 // ----- LCDPS bits --------------------
1122 unsigned char LP0:1;
1123 unsigned char LP1:1;
1124 unsigned char LP2:1;
1125 unsigned char LP3:1;
1127 unsigned char LCDA:1;
1128 unsigned char BIASMD:1;
1129 unsigned char WFT:1;
1132 extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits;
1134 #define LP0 LCDPS_bits.LP0
1135 #define LP1 LCDPS_bits.LP1
1136 #define LP2 LCDPS_bits.LP2
1137 #define LP3 LCDPS_bits.LP3
1138 #define WA LCDPS_bits.WA
1139 #define LCDA LCDPS_bits.LCDA
1140 #define BIASMD LCDPS_bits.BIASMD
1141 #define WFT LCDPS_bits.WFT
1143 // ----- LCDSE0 bits --------------------
1146 unsigned char SE0:1;
1147 unsigned char SE1:1;
1148 unsigned char SE2:1;
1149 unsigned char SE3:1;
1150 unsigned char SE4:1;
1151 unsigned char SE5:1;
1152 unsigned char SE6:1;
1153 unsigned char SE7:1;
1156 unsigned char SEGEN0:1;
1157 unsigned char SEGEN1:1;
1158 unsigned char SEGEN2:1;
1159 unsigned char SEGEN3:1;
1160 unsigned char SEGEN4:1;
1161 unsigned char SEGEN5:1;
1162 unsigned char SEGEN6:1;
1163 unsigned char SEGEN7:1;
1166 extern volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits;
1168 #define SE0 LCDSE0_bits.SE0
1169 #define SEGEN0 LCDSE0_bits.SEGEN0
1170 #define SE1 LCDSE0_bits.SE1
1171 #define SEGEN1 LCDSE0_bits.SEGEN1
1172 #define SE2 LCDSE0_bits.SE2
1173 #define SEGEN2 LCDSE0_bits.SEGEN2
1174 #define SE3 LCDSE0_bits.SE3
1175 #define SEGEN3 LCDSE0_bits.SEGEN3
1176 #define SE4 LCDSE0_bits.SE4
1177 #define SEGEN4 LCDSE0_bits.SEGEN4
1178 #define SE5 LCDSE0_bits.SE5
1179 #define SEGEN5 LCDSE0_bits.SEGEN5
1180 #define SE6 LCDSE0_bits.SE6
1181 #define SEGEN6 LCDSE0_bits.SEGEN6
1182 #define SE7 LCDSE0_bits.SE7
1183 #define SEGEN7 LCDSE0_bits.SEGEN7
1185 // ----- LCDSE1 bits --------------------
1188 unsigned char SE8:1;
1189 unsigned char SE9:1;
1190 unsigned char SE10:1;
1191 unsigned char SE11:1;
1192 unsigned char SE12:1;
1193 unsigned char SE13:1;
1194 unsigned char SE14:1;
1195 unsigned char SE15:1;
1198 unsigned char SEGEN8:1;
1199 unsigned char SEGEN9:1;
1200 unsigned char SEGEN10:1;
1201 unsigned char SEGEN11:1;
1202 unsigned char SEGEN12:1;
1203 unsigned char SEGEN13:1;
1204 unsigned char SEGEN14:1;
1205 unsigned char SEGEN15:1;
1208 extern volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits;
1210 #define SE8 LCDSE1_bits.SE8
1211 #define SEGEN8 LCDSE1_bits.SEGEN8
1212 #define SE9 LCDSE1_bits.SE9
1213 #define SEGEN9 LCDSE1_bits.SEGEN9
1214 #define SE10 LCDSE1_bits.SE10
1215 #define SEGEN10 LCDSE1_bits.SEGEN10
1216 #define SE11 LCDSE1_bits.SE11
1217 #define SEGEN11 LCDSE1_bits.SEGEN11
1218 #define SE12 LCDSE1_bits.SE12
1219 #define SEGEN12 LCDSE1_bits.SEGEN12
1220 #define SE13 LCDSE1_bits.SE13
1221 #define SEGEN13 LCDSE1_bits.SEGEN13
1222 #define SE14 LCDSE1_bits.SE14
1223 #define SEGEN14 LCDSE1_bits.SEGEN14
1224 #define SE15 LCDSE1_bits.SE15
1225 #define SEGEN15 LCDSE1_bits.SEGEN15
1227 // ----- LVDCON bits --------------------
1230 unsigned char LVDL0:1;
1231 unsigned char LVDL1:1;
1232 unsigned char LVDL2:1;
1234 unsigned char LVDEN:1;
1235 unsigned char IRVST:1;
1240 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
1242 #define LVDL0 LVDCON_bits.LVDL0
1243 #define LVDL1 LVDCON_bits.LVDL1
1244 #define LVDL2 LVDCON_bits.LVDL2
1245 #define LVDEN LVDCON_bits.LVDEN
1246 #define IRVST LVDCON_bits.IRVST
1248 // ----- OPTION_REG bits --------------------
1251 unsigned char PS0:1;
1252 unsigned char PS1:1;
1253 unsigned char PS2:1;
1254 unsigned char PSA:1;
1255 unsigned char T0SE:1;
1256 unsigned char T0CS:1;
1257 unsigned char INTEDG:1;
1258 unsigned char NOT_RBPU:1;
1260 } __OPTION_REG_bits_t;
1261 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
1263 #define PS0 OPTION_REG_bits.PS0
1264 #define PS1 OPTION_REG_bits.PS1
1265 #define PS2 OPTION_REG_bits.PS2
1266 #define PSA OPTION_REG_bits.PSA
1267 #define T0SE OPTION_REG_bits.T0SE
1268 #define T0CS OPTION_REG_bits.T0CS
1269 #define INTEDG OPTION_REG_bits.INTEDG
1270 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
1272 // ----- OSCCON bits --------------------
1275 unsigned char SCS:1;
1276 unsigned char LTS:1;
1277 unsigned char HTS:1;
1278 unsigned char OSTS:1;
1279 unsigned char IRCF0:1;
1280 unsigned char IRCF1:1;
1281 unsigned char IRCF2:1;
1285 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
1287 #define SCS OSCCON_bits.SCS
1288 #define LTS OSCCON_bits.LTS
1289 #define HTS OSCCON_bits.HTS
1290 #define OSTS OSCCON_bits.OSTS
1291 #define IRCF0 OSCCON_bits.IRCF0
1292 #define IRCF1 OSCCON_bits.IRCF1
1293 #define IRCF2 OSCCON_bits.IRCF2
1295 // ----- OSCTUNE bits --------------------
1298 unsigned char TUN0:1;
1299 unsigned char TUN1:1;
1300 unsigned char TUN2:1;
1301 unsigned char TUN3:1;
1302 unsigned char TUN4:1;
1308 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
1310 #define TUN0 OSCTUNE_bits.TUN0
1311 #define TUN1 OSCTUNE_bits.TUN1
1312 #define TUN2 OSCTUNE_bits.TUN2
1313 #define TUN3 OSCTUNE_bits.TUN3
1314 #define TUN4 OSCTUNE_bits.TUN4
1316 // ----- PCON bits --------------------
1319 unsigned char NOT_BO:1;
1320 unsigned char NOT_POR:1;
1323 unsigned char SBOREN:1;
1329 unsigned char NOT_BOR:1;
1339 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
1341 #define NOT_BO PCON_bits.NOT_BO
1342 #define NOT_BOR PCON_bits.NOT_BOR
1343 #define NOT_POR PCON_bits.NOT_POR
1344 #define SBOREN PCON_bits.SBOREN
1346 // ----- PIE1 bits --------------------
1349 unsigned char TMR1IE:1;
1350 unsigned char TMR2IE:1;
1351 unsigned char CCP1IE:1;
1352 unsigned char SSPIE:1;
1353 unsigned char TXIE:1;
1354 unsigned char RCIE:1;
1355 unsigned char ADIE:1;
1356 unsigned char EEIE:1;
1359 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
1361 #define TMR1IE PIE1_bits.TMR1IE
1362 #define TMR2IE PIE1_bits.TMR2IE
1363 #define CCP1IE PIE1_bits.CCP1IE
1364 #define SSPIE PIE1_bits.SSPIE
1365 #define TXIE PIE1_bits.TXIE
1366 #define RCIE PIE1_bits.RCIE
1367 #define ADIE PIE1_bits.ADIE
1368 #define EEIE PIE1_bits.EEIE
1370 // ----- PIE2 bits --------------------
1375 unsigned char LVDIE:1;
1377 unsigned char LCDIE:1;
1378 unsigned char C1IE:1;
1379 unsigned char C2IE:1;
1380 unsigned char OSFIE:1;
1383 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
1385 #define LVDIE PIE2_bits.LVDIE
1386 #define LCDIE PIE2_bits.LCDIE
1387 #define C1IE PIE2_bits.C1IE
1388 #define C2IE PIE2_bits.C2IE
1389 #define OSFIE PIE2_bits.OSFIE
1391 // ----- PIR1 bits --------------------
1394 unsigned char TMR1IF:1;
1395 unsigned char TMR2IF:1;
1396 unsigned char CCP1IF:1;
1397 unsigned char SSPIF:1;
1398 unsigned char TXIF:1;
1399 unsigned char RCIF:1;
1400 unsigned char ADIF:1;
1401 unsigned char EEIF:1;
1404 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
1406 #define TMR1IF PIR1_bits.TMR1IF
1407 #define TMR2IF PIR1_bits.TMR2IF
1408 #define CCP1IF PIR1_bits.CCP1IF
1409 #define SSPIF PIR1_bits.SSPIF
1410 #define TXIF PIR1_bits.TXIF
1411 #define RCIF PIR1_bits.RCIF
1412 #define ADIF PIR1_bits.ADIF
1413 #define EEIF PIR1_bits.EEIF
1415 // ----- PIR2 bits --------------------
1420 unsigned char LVDIF:1;
1422 unsigned char LCDIF:1;
1423 unsigned char C1IF:1;
1424 unsigned char C2IF:1;
1425 unsigned char OSFIF:1;
1428 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
1430 #define LVDIF PIR2_bits.LVDIF
1431 #define LCDIF PIR2_bits.LCDIF
1432 #define C1IF PIR2_bits.C1IF
1433 #define C2IF PIR2_bits.C2IF
1434 #define OSFIF PIR2_bits.OSFIF
1436 // ----- PORTA bits --------------------
1439 unsigned char RA0:1;
1440 unsigned char RA1:1;
1441 unsigned char RA2:1;
1442 unsigned char RA3:1;
1443 unsigned char RA4:1;
1444 unsigned char RA5:1;
1449 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
1451 #define RA0 PORTA_bits.RA0
1452 #define RA1 PORTA_bits.RA1
1453 #define RA2 PORTA_bits.RA2
1454 #define RA3 PORTA_bits.RA3
1455 #define RA4 PORTA_bits.RA4
1456 #define RA5 PORTA_bits.RA5
1458 // ----- PORTB bits --------------------
1461 unsigned char RB0:1;
1462 unsigned char RB1:1;
1463 unsigned char RB2:1;
1464 unsigned char RB3:1;
1465 unsigned char RB4:1;
1466 unsigned char RB5:1;
1467 unsigned char RB6:1;
1468 unsigned char RB7:1;
1471 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
1473 #define RB0 PORTB_bits.RB0
1474 #define RB1 PORTB_bits.RB1
1475 #define RB2 PORTB_bits.RB2
1476 #define RB3 PORTB_bits.RB3
1477 #define RB4 PORTB_bits.RB4
1478 #define RB5 PORTB_bits.RB5
1479 #define RB6 PORTB_bits.RB6
1480 #define RB7 PORTB_bits.RB7
1482 // ----- PORTC bits --------------------
1485 unsigned char RC0:1;
1486 unsigned char RC1:1;
1487 unsigned char RC2:1;
1488 unsigned char RC3:1;
1489 unsigned char RC4:1;
1490 unsigned char RC5:1;
1491 unsigned char RC6:1;
1492 unsigned char RC7:1;
1495 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
1497 #define RC0 PORTC_bits.RC0
1498 #define RC1 PORTC_bits.RC1
1499 #define RC2 PORTC_bits.RC2
1500 #define RC3 PORTC_bits.RC3
1501 #define RC4 PORTC_bits.RC4
1502 #define RC5 PORTC_bits.RC5
1503 #define RC6 PORTC_bits.RC6
1504 #define RC7 PORTC_bits.RC7
1506 // ----- PORTE bits --------------------
1509 unsigned char RE0:1;
1510 unsigned char RE1:1;
1511 unsigned char RE2:1;
1519 extern volatile __PORTE_bits_t __at(PORTE_ADDR) PORTE_bits;
1521 #define RE0 PORTE_bits.RE0
1522 #define RE1 PORTE_bits.RE1
1523 #define RE2 PORTE_bits.RE2
1525 // ----- RCSTA bits --------------------
1528 unsigned char RX9D:1;
1529 unsigned char OERR:1;
1530 unsigned char FERR:1;
1531 unsigned char ADDEN:1;
1532 unsigned char CREN:1;
1533 unsigned char SREN:1;
1534 unsigned char RX9:1;
1535 unsigned char SPEN:1;
1538 unsigned char RCD8:1;
1544 unsigned char RC9:1;
1554 unsigned char NOT_RC8:1;
1564 unsigned char RC8_9:1;
1568 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
1570 #define RX9D RCSTA_bits.RX9D
1571 #define RCD8 RCSTA_bits.RCD8
1572 #define OERR RCSTA_bits.OERR
1573 #define FERR RCSTA_bits.FERR
1574 #define ADDEN RCSTA_bits.ADDEN
1575 #define CREN RCSTA_bits.CREN
1576 #define SREN RCSTA_bits.SREN
1577 #define RX9 RCSTA_bits.RX9
1578 #define RC9 RCSTA_bits.RC9
1579 #define NOT_RC8 RCSTA_bits.NOT_RC8
1580 #define RC8_9 RCSTA_bits.RC8_9
1581 #define SPEN RCSTA_bits.SPEN
1583 // ----- SSPCON bits --------------------
1586 unsigned char SSPM0:1;
1587 unsigned char SSPM1:1;
1588 unsigned char SSPM2:1;
1589 unsigned char SSPM3:1;
1590 unsigned char CKP:1;
1591 unsigned char SSPEN:1;
1592 unsigned char SSPOV:1;
1593 unsigned char WCOL:1;
1596 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1598 #define SSPM0 SSPCON_bits.SSPM0
1599 #define SSPM1 SSPCON_bits.SSPM1
1600 #define SSPM2 SSPCON_bits.SSPM2
1601 #define SSPM3 SSPCON_bits.SSPM3
1602 #define CKP SSPCON_bits.CKP
1603 #define SSPEN SSPCON_bits.SSPEN
1604 #define SSPOV SSPCON_bits.SSPOV
1605 #define WCOL SSPCON_bits.WCOL
1607 // ----- SSPSTAT bits --------------------
1616 unsigned char CKE:1;
1617 unsigned char SMP:1;
1622 unsigned char I2C_READ:1;
1623 unsigned char I2C_START:1;
1624 unsigned char I2C_STOP:1;
1625 unsigned char I2C_DATA:1;
1632 unsigned char NOT_W:1;
1635 unsigned char NOT_A:1;
1642 unsigned char NOT_WRITE:1;
1645 unsigned char NOT_ADDRESS:1;
1652 unsigned char R_W:1;
1655 unsigned char D_A:1;
1662 unsigned char READ_WRITE:1;
1665 unsigned char DATA_ADDRESS:1;
1670 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1672 #define BF SSPSTAT_bits.BF
1673 #define UA SSPSTAT_bits.UA
1674 #define R SSPSTAT_bits.R
1675 #define I2C_READ SSPSTAT_bits.I2C_READ
1676 #define NOT_W SSPSTAT_bits.NOT_W
1677 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1678 #define R_W SSPSTAT_bits.R_W
1679 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1680 #define S SSPSTAT_bits.S
1681 #define I2C_START SSPSTAT_bits.I2C_START
1682 #define P SSPSTAT_bits.P
1683 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1684 #define D SSPSTAT_bits.D
1685 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1686 #define NOT_A SSPSTAT_bits.NOT_A
1687 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1688 #define D_A SSPSTAT_bits.D_A
1689 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1690 #define CKE SSPSTAT_bits.CKE
1691 #define SMP SSPSTAT_bits.SMP
1693 // ----- STATUS bits --------------------
1699 unsigned char NOT_PD:1;
1700 unsigned char NOT_TO:1;
1701 unsigned char RP0:1;
1702 unsigned char RP1:1;
1703 unsigned char IRP:1;
1706 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1708 #define C STATUS_bits.C
1709 #define DC STATUS_bits.DC
1710 #define Z STATUS_bits.Z
1711 #define NOT_PD STATUS_bits.NOT_PD
1712 #define NOT_TO STATUS_bits.NOT_TO
1713 #define RP0 STATUS_bits.RP0
1714 #define RP1 STATUS_bits.RP1
1715 #define IRP STATUS_bits.IRP
1717 // ----- T1CON bits --------------------
1720 unsigned char TMR1ON:1;
1721 unsigned char TMR1CS:1;
1722 unsigned char NOT_T1SYNC:1;
1723 unsigned char T1OSCEN:1;
1724 unsigned char T1CKPS0:1;
1725 unsigned char T1CKPS1:1;
1726 unsigned char T1GE:1;
1727 unsigned char T1GINV:1;
1732 unsigned char T1INSYNC:1;
1742 unsigned char T1SYNC:1;
1750 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1752 #define TMR1ON T1CON_bits.TMR1ON
1753 #define TMR1CS T1CON_bits.TMR1CS
1754 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1755 #define T1INSYNC T1CON_bits.T1INSYNC
1756 #define T1SYNC T1CON_bits.T1SYNC
1757 #define T1OSCEN T1CON_bits.T1OSCEN
1758 #define T1CKPS0 T1CON_bits.T1CKPS0
1759 #define T1CKPS1 T1CON_bits.T1CKPS1
1760 #define T1GE T1CON_bits.T1GE
1761 #define T1GINV T1CON_bits.T1GINV
1763 // ----- T2CON bits --------------------
1766 unsigned char T2CKPS0:1;
1767 unsigned char T2CKPS1:1;
1768 unsigned char TMR2ON:1;
1769 unsigned char TOUTPS0:1;
1770 unsigned char TOUTPS1:1;
1771 unsigned char TOUTPS2:1;
1772 unsigned char TOUTPS3:1;
1776 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1778 #define T2CKPS0 T2CON_bits.T2CKPS0
1779 #define T2CKPS1 T2CON_bits.T2CKPS1
1780 #define TMR2ON T2CON_bits.TMR2ON
1781 #define TOUTPS0 T2CON_bits.TOUTPS0
1782 #define TOUTPS1 T2CON_bits.TOUTPS1
1783 #define TOUTPS2 T2CON_bits.TOUTPS2
1784 #define TOUTPS3 T2CON_bits.TOUTPS3
1786 // ----- TRISA bits --------------------
1789 unsigned char TRISA0:1;
1790 unsigned char TRISA1:1;
1791 unsigned char TRISA2:1;
1792 unsigned char TRISA3:1;
1793 unsigned char TRISA4:1;
1794 unsigned char TRISA5:1;
1799 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1801 #define TRISA0 TRISA_bits.TRISA0
1802 #define TRISA1 TRISA_bits.TRISA1
1803 #define TRISA2 TRISA_bits.TRISA2
1804 #define TRISA3 TRISA_bits.TRISA3
1805 #define TRISA4 TRISA_bits.TRISA4
1806 #define TRISA5 TRISA_bits.TRISA5
1808 // ----- TRISB bits --------------------
1811 unsigned char TRISB0:1;
1812 unsigned char TRISB1:1;
1813 unsigned char TRISB2:1;
1814 unsigned char TRISB3:1;
1815 unsigned char TRISB4:1;
1816 unsigned char TRISB5:1;
1817 unsigned char TRISB6:1;
1818 unsigned char TRISB7:1;
1821 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1823 #define TRISB0 TRISB_bits.TRISB0
1824 #define TRISB1 TRISB_bits.TRISB1
1825 #define TRISB2 TRISB_bits.TRISB2
1826 #define TRISB3 TRISB_bits.TRISB3
1827 #define TRISB4 TRISB_bits.TRISB4
1828 #define TRISB5 TRISB_bits.TRISB5
1829 #define TRISB6 TRISB_bits.TRISB6
1830 #define TRISB7 TRISB_bits.TRISB7
1832 // ----- TRISC bits --------------------
1835 unsigned char TRISC0:1;
1836 unsigned char TRISC1:1;
1837 unsigned char TRISC2:1;
1838 unsigned char TRISC3:1;
1839 unsigned char TRISC4:1;
1840 unsigned char TRISC5:1;
1841 unsigned char TRISC6:1;
1842 unsigned char TRISC7:1;
1845 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1847 #define TRISC0 TRISC_bits.TRISC0
1848 #define TRISC1 TRISC_bits.TRISC1
1849 #define TRISC2 TRISC_bits.TRISC2
1850 #define TRISC3 TRISC_bits.TRISC3
1851 #define TRISC4 TRISC_bits.TRISC4
1852 #define TRISC5 TRISC_bits.TRISC5
1853 #define TRISC6 TRISC_bits.TRISC6
1854 #define TRISC7 TRISC_bits.TRISC7
1856 // ----- TRISE bits --------------------
1859 unsigned char TRISE0:1;
1860 unsigned char TRISE1:1;
1861 unsigned char TRISE2:1;
1869 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1871 #define TRISE0 TRISE_bits.TRISE0
1872 #define TRISE1 TRISE_bits.TRISE1
1873 #define TRISE2 TRISE_bits.TRISE2
1875 // ----- TXSTA bits --------------------
1878 unsigned char TX9D:1;
1879 unsigned char TRMT:1;
1880 unsigned char BRGH:1;
1882 unsigned char SYNC:1;
1883 unsigned char TXEN:1;
1884 unsigned char TX9:1;
1885 unsigned char CSRC:1;
1888 unsigned char TXD8:1;
1894 unsigned char NOT_TX8:1;
1904 unsigned char TX8_9:1;
1908 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1910 #define TX9D TXSTA_bits.TX9D
1911 #define TXD8 TXSTA_bits.TXD8
1912 #define TRMT TXSTA_bits.TRMT
1913 #define BRGH TXSTA_bits.BRGH
1914 #define SYNC TXSTA_bits.SYNC
1915 #define TXEN TXSTA_bits.TXEN
1916 #define TX9 TXSTA_bits.TX9
1917 #define NOT_TX8 TXSTA_bits.NOT_TX8
1918 #define TX8_9 TXSTA_bits.TX8_9
1919 #define CSRC TXSTA_bits.CSRC
1921 // ----- VRCON bits --------------------
1924 unsigned char VR0:1;
1925 unsigned char VR1:1;
1926 unsigned char VR2:1;
1927 unsigned char VR3:1;
1929 unsigned char VRR:1;
1931 unsigned char VREN:1;
1934 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1936 #define VR0 VRCON_bits.VR0
1937 #define VR1 VRCON_bits.VR1
1938 #define VR2 VRCON_bits.VR2
1939 #define VR3 VRCON_bits.VR3
1940 #define VRR VRCON_bits.VRR
1941 #define VREN VRCON_bits.VREN
1943 // ----- WDTCON bits --------------------
1946 unsigned char SWDTEN:1;
1947 unsigned char WDTPS0:1;
1948 unsigned char WDTPS1:1;
1949 unsigned char WDTPS2:1;
1950 unsigned char WDTPS3:1;
1956 unsigned char SWDTE:1;
1966 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1968 #define SWDTEN WDTCON_bits.SWDTEN
1969 #define SWDTE WDTCON_bits.SWDTE
1970 #define WDTPS0 WDTCON_bits.WDTPS0
1971 #define WDTPS1 WDTCON_bits.WDTPS1
1972 #define WDTPS2 WDTCON_bits.WDTPS2
1973 #define WDTPS3 WDTCON_bits.WDTPS3
1975 // ----- WPU bits --------------------
1978 unsigned char WPU0:1;
1979 unsigned char WPU1:1;
1980 unsigned char WPU2:1;
1981 unsigned char WPU3:1;
1982 unsigned char WPU4:1;
1983 unsigned char WPU5:1;
1984 unsigned char WPU6:1;
1985 unsigned char WPU7:1;
1988 extern volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits;
1990 #define WPU0 WPU_bits.WPU0
1991 #define WPU1 WPU_bits.WPU1
1992 #define WPU2 WPU_bits.WPU2
1993 #define WPU3 WPU_bits.WPU3
1994 #define WPU4 WPU_bits.WPU4
1995 #define WPU5 WPU_bits.WPU5
1996 #define WPU6 WPU_bits.WPU6
1997 #define WPU7 WPU_bits.WPU7
1999 // ----- WPUB bits --------------------
2002 unsigned char WPUB0:1;
2003 unsigned char WPUB1:1;
2004 unsigned char WPUB2:1;
2005 unsigned char WPUB3:1;
2006 unsigned char WPUB4:1;
2007 unsigned char WPUB5:1;
2008 unsigned char WPUB6:1;
2009 unsigned char WPUB7:1;
2012 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
2014 #define WPUB0 WPUB_bits.WPUB0
2015 #define WPUB1 WPUB_bits.WPUB1
2016 #define WPUB2 WPUB_bits.WPUB2
2017 #define WPUB3 WPUB_bits.WPUB3
2018 #define WPUB4 WPUB_bits.WPUB4
2019 #define WPUB5 WPUB_bits.WPUB5
2020 #define WPUB6 WPUB_bits.WPUB6
2021 #define WPUB7 WPUB_bits.WPUB7