2 // Register Declarations for Microchip 16F886 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTE_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define PIR1_ADDR 0x000C
40 #define PIR2_ADDR 0x000D
41 #define TMR1L_ADDR 0x000E
42 #define TMR1H_ADDR 0x000F
43 #define T1CON_ADDR 0x0010
44 #define TMR2_ADDR 0x0011
45 #define T2CON_ADDR 0x0012
46 #define SSPBUF_ADDR 0x0013
47 #define SSPCON_ADDR 0x0014
48 #define CCPR1L_ADDR 0x0015
49 #define CCPR1H_ADDR 0x0016
50 #define CCP1CON_ADDR 0x0017
51 #define RCSTA_ADDR 0x0018
52 #define TXREG_ADDR 0x0019
53 #define RCREG_ADDR 0x001A
54 #define CCPR2L_ADDR 0x001B
55 #define CCPR2H_ADDR 0x001C
56 #define CCP2CON_ADDR 0x001D
57 #define ADRESH_ADDR 0x001E
58 #define ADCON0_ADDR 0x001F
59 #define OPTION_REG_ADDR 0x0081
60 #define TRISA_ADDR 0x0085
61 #define TRISB_ADDR 0x0086
62 #define TRISC_ADDR 0x0087
63 #define TRISE_ADDR 0x0089
64 #define PIE1_ADDR 0x008C
65 #define PIE2_ADDR 0x008D
66 #define PCON_ADDR 0x008E
67 #define OSCCON_ADDR 0x008F
68 #define OSCTUNE_ADDR 0x0090
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define WPUB_ADDR 0x0095
74 #define IOCB_ADDR 0x0096
75 #define VRCON_ADDR 0x0097
76 #define TXSTA_ADDR 0x0098
77 #define SPBRG_ADDR 0x0099
78 #define SPBRGH_ADDR 0x009A
79 #define PWM1CON_ADDR 0x009B
80 #define ECCPAS_ADDR 0x009C
81 #define PSTRCON_ADDR 0x009D
82 #define ADRESL_ADDR 0x009E
83 #define ADCON1_ADDR 0x009F
84 #define WDTCON_ADDR 0x0105
85 #define CM1CON0_ADDR 0x0107
86 #define CM2CON0_ADDR 0x0108
87 #define CM2CON1_ADDR 0x0109
88 #define EEDATA_ADDR 0x010C
89 #define EEADR_ADDR 0x010D
90 #define EEDATH_ADDR 0x010E
91 #define EEADRH_ADDR 0x010F
92 #define SRCON_ADDR 0x0185
93 #define BAUDCTL_ADDR 0x0187
94 #define ANSEL_ADDR 0x0188
95 #define ANSELH_ADDR 0x0189
96 #define EECON1_ADDR 0x018C
97 #define EECON2_ADDR 0x018D
100 // Memory organization.
106 // P16F886.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
109 // This header file defines configurations, registers, and other useful bits of
110 // information for the PIC16F886 microcontroller. These names are taken to match
111 // the data sheets as closely as possible.
113 // Note that the processor must be selected before this file is
114 // included. The processor may be selected the following ways:
116 // 1. Command line switch:
117 // C:\ MPASM MYFILE.ASM /PIC16F886
118 // 2. LIST directive in the source file
120 // 3. Processor Type entry in the MPASM full-screen interface
122 //==========================================================================
126 //==========================================================================
128 //1.00 11/18/05 Original
130 //==========================================================================
134 //==========================================================================
137 // MESSG "Processor-header file mismatch. Verify selected processor."
140 //==========================================================================
142 // Register Definitions
144 //==========================================================================
149 //----- Register Files------------------------------------------------------
151 extern __sfr __at (INDF_ADDR) INDF;
152 extern __sfr __at (TMR0_ADDR) TMR0;
153 extern __sfr __at (PCL_ADDR) PCL;
154 extern __sfr __at (STATUS_ADDR) STATUS;
155 extern __sfr __at (FSR_ADDR) FSR;
156 extern __sfr __at (PORTA_ADDR) PORTA;
157 extern __sfr __at (PORTB_ADDR) PORTB;
158 extern __sfr __at (PORTC_ADDR) PORTC;
160 extern __sfr __at (PORTE_ADDR) PORTE;
161 extern __sfr __at (PCLATH_ADDR) PCLATH;
162 extern __sfr __at (INTCON_ADDR) INTCON;
163 extern __sfr __at (PIR1_ADDR) PIR1;
164 extern __sfr __at (PIR2_ADDR) PIR2;
165 extern __sfr __at (TMR1L_ADDR) TMR1L;
166 extern __sfr __at (TMR1H_ADDR) TMR1H;
167 extern __sfr __at (T1CON_ADDR) T1CON;
168 extern __sfr __at (TMR2_ADDR) TMR2;
169 extern __sfr __at (T2CON_ADDR) T2CON;
170 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
171 extern __sfr __at (SSPCON_ADDR) SSPCON;
172 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
173 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
174 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
175 extern __sfr __at (RCSTA_ADDR) RCSTA;
176 extern __sfr __at (TXREG_ADDR) TXREG;
177 extern __sfr __at (RCREG_ADDR) RCREG;
178 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
179 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
180 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
181 extern __sfr __at (ADRESH_ADDR) ADRESH;
182 extern __sfr __at (ADCON0_ADDR) ADCON0;
184 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
186 extern __sfr __at (TRISA_ADDR) TRISA;
187 extern __sfr __at (TRISB_ADDR) TRISB;
188 extern __sfr __at (TRISC_ADDR) TRISC;
190 extern __sfr __at (TRISE_ADDR) TRISE;
192 extern __sfr __at (PIE1_ADDR) PIE1;
193 extern __sfr __at (PIE2_ADDR) PIE2;
194 extern __sfr __at (PCON_ADDR) PCON;
195 extern __sfr __at (OSCCON_ADDR) OSCCON;
196 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
197 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
198 extern __sfr __at (PR2_ADDR) PR2;
199 extern __sfr __at (SSPADD_ADDR) SSPADD;
200 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
201 extern __sfr __at (WPUB_ADDR) WPUB;
202 extern __sfr __at (IOCB_ADDR) IOCB;
203 extern __sfr __at (VRCON_ADDR) VRCON;
204 extern __sfr __at (TXSTA_ADDR) TXSTA;
205 extern __sfr __at (SPBRG_ADDR) SPBRG;
206 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
207 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
208 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
209 extern __sfr __at (PSTRCON_ADDR) PSTRCON;
210 extern __sfr __at (ADRESL_ADDR) ADRESL;
211 extern __sfr __at (ADCON1_ADDR) ADCON1;
213 extern __sfr __at (WDTCON_ADDR) WDTCON;
215 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
216 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
217 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
219 extern __sfr __at (EEDATA_ADDR) EEDATA;
220 extern __sfr __at (EEADR_ADDR) EEADR;
221 extern __sfr __at (EEDATH_ADDR) EEDATH;
222 extern __sfr __at (EEADRH_ADDR) EEADRH;
224 extern __sfr __at (SRCON_ADDR) SRCON;
226 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
227 extern __sfr __at (ANSEL_ADDR) ANSEL;
228 extern __sfr __at (ANSELH_ADDR) ANSELH;
230 extern __sfr __at (EECON1_ADDR) EECON1;
231 extern __sfr __at (EECON2_ADDR) EECON2;
233 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
234 //----- STATUS Bits --------------------------------------------------------
237 //----- INTCON Bits --------------------------------------------------------
240 //----- PIR1 Bits ----------------------------------------------------------
243 //----- PIR2 Bits ----------------------------------------------------------
246 //----- T1CON Bits ---------------------------------------------------------
249 //----- T2CON Bits ---------------------------------------------------------
252 //----- SSPCON Bits --------------------------------------------------------
255 //----- CCP1CON Bits -------------------------------------------------------
258 //----- RCSTA Bits ---------------------------------------------------------
261 //----- CCP2CON Bits -------------------------------------------------------
264 //----- ADCON0 Bits --------------------------------------------------------
267 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
268 //----- OPTION_REG Bits -----------------------------------------------------
271 //----- PIE1 Bits ----------------------------------------------------------
274 //----- PIE2 Bits ----------------------------------------------------------
277 //----- PCON Bits ----------------------------------------------------------
280 //----- OSCCON Bits --------------------------------------------------------
283 //----- OSCTUNE Bits -------------------------------------------------------
286 //----- SSPCON2 Bits --------------------------------------------------------
289 //----- SSPSTAT Bits -------------------------------------------------------
292 //----- WPUB Bits ----------------------------------------------------------
295 //----- IOCB Bits ----------------------------------------------------------
298 //----- VRCON Bits ---------------------------------------------------------
301 //----- TXSTA Bits ---------------------------------------------------------
304 //----- SPBRG Bits -------------------------------------------------------
307 //----- SPBRGH Bits -------------------------------------------------------
310 //----- PWM1CON Bits -------------------------------------------------------
313 //----- ECCPAS Bits --------------------------------------------------------
316 //----- PSTRCON -------------------------------------------------------------
319 //----- ADCON1 -------------------------------------------------------------
322 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
323 //----- WDTCON Bits --------------------------------------------------------
326 //----- CM1CON0 Bits -------------------------------------------------------
330 //----- CM2CON0 Bits -------------------------------------------------------
334 //----- CM2CON1 Bits -------------------------------------------------------
338 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
339 //----- SRCON ---------------------------------------------------------------
343 //----- BAUDCTL Bits -------------------------------------------------------
348 //----- ANSEL --------------------------------------------------------------
351 //----- ANSELH -------------------------------------------------------------
354 //----- EECON1 Bits --------------------------------------------------------
358 //==========================================================================
362 //==========================================================================
365 // __BADRAM H'18E'-H'18F'
367 //==========================================================================
369 // Configuration Bits
371 //==========================================================================
372 #define _CONFIG1 0x2007
373 #define _CONFIG2 0x2008
375 //----- Configuration Word1 ------------------------------------------------
377 #define _LVP_ON 0x3FFF
378 #define _LVP_OFF 0x2FFF
379 #define _FCMEN_ON 0x3FFF
380 #define _FCMEN_OFF 0x37FF
381 #define _IESO_ON 0x3FFF
382 #define _IESO_OFF 0x3BFF
383 #define _BOR_ON 0x3FFF
384 #define _BOR_NSLEEP 0x3EFF
385 #define _BOR_SBODEN 0x3DFF
386 #define _BOR_OFF 0x3CFF
387 #define _CPD_ON 0x3F7F
388 #define _CPD_OFF 0x3FFF
389 #define _CP_ON 0x3FBF
390 #define _CP_OFF 0x3FFF
391 #define _MCLRE_ON 0x3FFF
392 #define _MCLRE_OFF 0x3FDF
393 #define _PWRTE_ON 0x3FEF
394 #define _PWRTE_OFF 0x3FFF
395 #define _WDT_ON 0x3FFF
396 #define _WDT_OFF 0x3FF7
397 #define _LP_OSC 0x3FF8
398 #define _XT_OSC 0x3FF9
399 #define _HS_OSC 0x3FFA
400 #define _EC_OSC 0x3FFB
401 #define _INTRC_OSC_NOCLKOUT 0x3FFC
402 #define _INTRC_OSC_CLKOUT 0x3FFD
403 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
404 #define _EXTRC_OSC_CLKOUT 0x3FFF
405 #define _INTOSCIO 0x3FFC
406 #define _INTOSC 0x3FFD
407 #define _EXTRCIO 0x3FFE
408 #define _EXTRC 0x3FFF
410 //----- Configuration Word2 ------------------------------------------------
412 #define _WRT_OFF 0x3FFF // No prog memmory write protection
413 #define _WRT_256 0x3DFF // First 256 prog memmory write protected
414 #define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected
415 #define _WRT_HALF 0x39FF // First half memmory write protected
417 #define _BOR21V 0x3EFF
418 #define _BOR40V 0x3FFF
422 // ----- ADCON0 bits --------------------
425 unsigned char ADON:1;
427 unsigned char CHS0:1;
428 unsigned char CHS1:1;
429 unsigned char CHS2:1;
430 unsigned char CHS3:1;
431 unsigned char ADCS0:1;
432 unsigned char ADCS1:1;
436 unsigned char NOT_DONE:1;
446 unsigned char GO_DONE:1;
455 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
457 #define ADON ADCON0_bits.ADON
458 #define GO ADCON0_bits.GO
459 #define NOT_DONE ADCON0_bits.NOT_DONE
460 #define GO_DONE ADCON0_bits.GO_DONE
461 #define CHS0 ADCON0_bits.CHS0
462 #define CHS1 ADCON0_bits.CHS1
463 #define CHS2 ADCON0_bits.CHS2
464 #define CHS3 ADCON0_bits.CHS3
465 #define ADCS0 ADCON0_bits.ADCS0
466 #define ADCS1 ADCON0_bits.ADCS1
468 // ----- ADCON1 bits --------------------
475 unsigned char VCFG1:1;
476 unsigned char VCFG0:1;
478 unsigned char ADFM:1;
481 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
483 #define VCFG1 ADCON1_bits.VCFG1
484 #define VCFG0 ADCON1_bits.VCFG0
485 #define ADFM ADCON1_bits.ADFM
487 // ----- ANSEL bits --------------------
490 unsigned char ANS0:1;
491 unsigned char ANS1:1;
492 unsigned char ANS2:1;
493 unsigned char ANS3:1;
494 unsigned char ANS4:1;
500 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
502 #define ANS0 ANSEL_bits.ANS0
503 #define ANS1 ANSEL_bits.ANS1
504 #define ANS2 ANSEL_bits.ANS2
505 #define ANS3 ANSEL_bits.ANS3
506 #define ANS4 ANSEL_bits.ANS4
508 // ----- ANSELH bits --------------------
511 unsigned char ANS8:1;
512 unsigned char ANS9:1;
513 unsigned char ANS10:1;
514 unsigned char ANS11:1;
515 unsigned char ANS12:1;
516 unsigned char ANS13:1;
521 extern volatile __ANSELH_bits_t __at(ANSELH_ADDR) ANSELH_bits;
523 #define ANS8 ANSELH_bits.ANS8
524 #define ANS9 ANSELH_bits.ANS9
525 #define ANS10 ANSELH_bits.ANS10
526 #define ANS11 ANSELH_bits.ANS11
527 #define ANS12 ANSELH_bits.ANS12
528 #define ANS13 ANSELH_bits.ANS13
530 // ----- BAUDCTL bits --------------------
533 unsigned char ABDEN:1;
536 unsigned char BRG16:1;
537 unsigned char SCKP:1;
539 unsigned char RCIDL:1;
540 unsigned char ABDOVF:1;
543 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
545 #define ABDEN BAUDCTL_bits.ABDEN
546 #define WUE BAUDCTL_bits.WUE
547 #define BRG16 BAUDCTL_bits.BRG16
548 #define SCKP BAUDCTL_bits.SCKP
549 #define RCIDL BAUDCTL_bits.RCIDL
550 #define ABDOVF BAUDCTL_bits.ABDOVF
552 // ----- CCP1CON bits --------------------
555 unsigned char CCP1M0:1;
556 unsigned char CCP1M1:1;
557 unsigned char CCP1M2:1;
558 unsigned char CCP1M3:1;
559 unsigned char DC1B0:1;
560 unsigned char DC1B1:1;
561 unsigned char P1M0:1;
562 unsigned char P1M1:1;
569 unsigned char CCP1Y:1;
570 unsigned char CCP1X:1;
575 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
577 #define CCP1M0 CCP1CON_bits.CCP1M0
578 #define CCP1M1 CCP1CON_bits.CCP1M1
579 #define CCP1M2 CCP1CON_bits.CCP1M2
580 #define CCP1M3 CCP1CON_bits.CCP1M3
581 #define DC1B0 CCP1CON_bits.DC1B0
582 #define CCP1Y CCP1CON_bits.CCP1Y
583 #define DC1B1 CCP1CON_bits.DC1B1
584 #define CCP1X CCP1CON_bits.CCP1X
585 #define P1M0 CCP1CON_bits.P1M0
586 #define P1M1 CCP1CON_bits.P1M1
588 // ----- CCP2CON bits --------------------
591 unsigned char CCP2M0:1;
592 unsigned char CCP2M1:1;
593 unsigned char CCP2M2:1;
594 unsigned char CCP2M3:1;
595 unsigned char CCP2Y:1;
596 unsigned char CCP2X:1;
605 unsigned char DC2B0:1;
606 unsigned char DC2B1:1;
611 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
613 #define CCP2M0 CCP2CON_bits.CCP2M0
614 #define CCP2M1 CCP2CON_bits.CCP2M1
615 #define CCP2M2 CCP2CON_bits.CCP2M2
616 #define CCP2M3 CCP2CON_bits.CCP2M3
617 #define CCP2Y CCP2CON_bits.CCP2Y
618 #define DC2B0 CCP2CON_bits.DC2B0
619 #define CCP2X CCP2CON_bits.CCP2X
620 #define DC2B1 CCP2CON_bits.DC2B1
622 // ----- CM1CON0 bits --------------------
625 unsigned char C1CH0:1;
626 unsigned char C1CH1:1;
629 unsigned char C1POL:1;
630 unsigned char C1OE:1;
631 unsigned char C1OUT:1;
632 unsigned char C1ON:1;
635 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
637 #define C1CH0 CM1CON0_bits.C1CH0
638 #define C1CH1 CM1CON0_bits.C1CH1
639 #define C1R CM1CON0_bits.C1R
640 #define C1POL CM1CON0_bits.C1POL
641 #define C1OE CM1CON0_bits.C1OE
642 #define C1OUT CM1CON0_bits.C1OUT
643 #define C1ON CM1CON0_bits.C1ON
645 // ----- CM2CON0 bits --------------------
648 unsigned char C2CH0:1;
649 unsigned char C2CH1:1;
652 unsigned char C2POL:1;
653 unsigned char C2OE:1;
654 unsigned char C2OUT:1;
655 unsigned char C2ON:1;
658 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
660 #define C2CH0 CM2CON0_bits.C2CH0
661 #define C2CH1 CM2CON0_bits.C2CH1
662 #define C2R CM2CON0_bits.C2R
663 #define C2POL CM2CON0_bits.C2POL
664 #define C2OE CM2CON0_bits.C2OE
665 #define C2OUT CM2CON0_bits.C2OUT
666 #define C2ON CM2CON0_bits.C2ON
668 // ----- CM2CON1 bits --------------------
671 unsigned char C2SYNC:1;
672 unsigned char T1GSS:1;
675 unsigned char C2RSEL:1;
676 unsigned char C1RSEL:1;
677 unsigned char MC2OUT:1;
678 unsigned char MC1OUT:1;
681 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
683 #define C2SYNC CM2CON1_bits.C2SYNC
684 #define T1GSS CM2CON1_bits.T1GSS
685 #define C2RSEL CM2CON1_bits.C2RSEL
686 #define C1RSEL CM2CON1_bits.C1RSEL
687 #define MC2OUT CM2CON1_bits.MC2OUT
688 #define MC1OUT CM2CON1_bits.MC1OUT
690 // ----- ECCPAS bits --------------------
693 unsigned char PSSBD0:1;
694 unsigned char PSSBD1:1;
695 unsigned char PSSAC0:1;
696 unsigned char PSSAC1:1;
697 unsigned char ECCPAS0:1;
698 unsigned char ECCPAS1:1;
699 unsigned char ECCPAS2:1;
700 unsigned char ECCPASE:1;
703 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
705 #define PSSBD0 ECCPAS_bits.PSSBD0
706 #define PSSBD1 ECCPAS_bits.PSSBD1
707 #define PSSAC0 ECCPAS_bits.PSSAC0
708 #define PSSAC1 ECCPAS_bits.PSSAC1
709 #define ECCPAS0 ECCPAS_bits.ECCPAS0
710 #define ECCPAS1 ECCPAS_bits.ECCPAS1
711 #define ECCPAS2 ECCPAS_bits.ECCPAS2
712 #define ECCPASE ECCPAS_bits.ECCPASE
714 // ----- EECON1 bits --------------------
719 unsigned char WREN:1;
720 unsigned char WRERR:1;
724 unsigned char EEPGD:1;
727 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
729 #define RD EECON1_bits.RD
730 #define WR EECON1_bits.WR
731 #define WREN EECON1_bits.WREN
732 #define WRERR EECON1_bits.WRERR
733 #define EEPGD EECON1_bits.EEPGD
735 // ----- INTCON bits --------------------
738 unsigned char RBIF:1;
739 unsigned char INTF:1;
740 unsigned char T0IF:1;
741 unsigned char RBIE:1;
742 unsigned char INTE:1;
743 unsigned char T0IE:1;
744 unsigned char PEIE:1;
750 unsigned char TMR0IF:1;
753 unsigned char TMR0IE:1;
758 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
760 #define RBIF INTCON_bits.RBIF
761 #define INTF INTCON_bits.INTF
762 #define T0IF INTCON_bits.T0IF
763 #define TMR0IF INTCON_bits.TMR0IF
764 #define RBIE INTCON_bits.RBIE
765 #define INTE INTCON_bits.INTE
766 #define T0IE INTCON_bits.T0IE
767 #define TMR0IE INTCON_bits.TMR0IE
768 #define PEIE INTCON_bits.PEIE
769 #define GIE INTCON_bits.GIE
771 // ----- IOCB bits --------------------
774 unsigned char IOCB0:1;
775 unsigned char IOCB1:1;
776 unsigned char IOCB2:1;
777 unsigned char IOCB3:1;
778 unsigned char IOCB4:1;
779 unsigned char IOCB5:1;
780 unsigned char IOCB6:1;
781 unsigned char IOCB7:1;
784 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
786 #define IOCB0 IOCB_bits.IOCB0
787 #define IOCB1 IOCB_bits.IOCB1
788 #define IOCB2 IOCB_bits.IOCB2
789 #define IOCB3 IOCB_bits.IOCB3
790 #define IOCB4 IOCB_bits.IOCB4
791 #define IOCB5 IOCB_bits.IOCB5
792 #define IOCB6 IOCB_bits.IOCB6
793 #define IOCB7 IOCB_bits.IOCB7
795 // ----- OPTION_REG bits --------------------
802 unsigned char T0SE:1;
803 unsigned char T0CS:1;
804 unsigned char INTEDG:1;
805 unsigned char NOT_RBPU:1;
807 } __OPTION_REG_bits_t;
808 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
810 #define PS0 OPTION_REG_bits.PS0
811 #define PS1 OPTION_REG_bits.PS1
812 #define PS2 OPTION_REG_bits.PS2
813 #define PSA OPTION_REG_bits.PSA
814 #define T0SE OPTION_REG_bits.T0SE
815 #define T0CS OPTION_REG_bits.T0CS
816 #define INTEDG OPTION_REG_bits.INTEDG
817 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
819 // ----- OSCCON bits --------------------
825 unsigned char OSTS:1;
826 unsigned char IRCF0:1;
827 unsigned char IRCF1:1;
828 unsigned char IRCF2:1;
832 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
834 #define SCS OSCCON_bits.SCS
835 #define LTS OSCCON_bits.LTS
836 #define HTS OSCCON_bits.HTS
837 #define OSTS OSCCON_bits.OSTS
838 #define IRCF0 OSCCON_bits.IRCF0
839 #define IRCF1 OSCCON_bits.IRCF1
840 #define IRCF2 OSCCON_bits.IRCF2
842 // ----- OSCTUNE bits --------------------
845 unsigned char TUN0:1;
846 unsigned char TUN1:1;
847 unsigned char TUN2:1;
848 unsigned char TUN3:1;
849 unsigned char TUN4:1;
855 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
857 #define TUN0 OSCTUNE_bits.TUN0
858 #define TUN1 OSCTUNE_bits.TUN1
859 #define TUN2 OSCTUNE_bits.TUN2
860 #define TUN3 OSCTUNE_bits.TUN3
861 #define TUN4 OSCTUNE_bits.TUN4
863 // ----- PCON bits --------------------
866 unsigned char NOT_BO:1;
867 unsigned char NOT_POR:1;
870 unsigned char SBOREN:1;
871 unsigned char ULPWUE:1;
876 unsigned char NOT_BOR:1;
886 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
888 #define NOT_BO PCON_bits.NOT_BO
889 #define NOT_BOR PCON_bits.NOT_BOR
890 #define NOT_POR PCON_bits.NOT_POR
891 #define SBOREN PCON_bits.SBOREN
892 #define ULPWUE PCON_bits.ULPWUE
894 // ----- PIE1 bits --------------------
897 unsigned char TMR1IE:1;
898 unsigned char TMR2IE:1;
899 unsigned char CCP1IE:1;
900 unsigned char SSPIE:1;
901 unsigned char TXIE:1;
902 unsigned char RCIE:1;
903 unsigned char ADIE:1;
907 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
909 #define TMR1IE PIE1_bits.TMR1IE
910 #define TMR2IE PIE1_bits.TMR2IE
911 #define CCP1IE PIE1_bits.CCP1IE
912 #define SSPIE PIE1_bits.SSPIE
913 #define TXIE PIE1_bits.TXIE
914 #define RCIE PIE1_bits.RCIE
915 #define ADIE PIE1_bits.ADIE
917 // ----- PIE2 bits --------------------
920 unsigned char CCP2IE:1;
922 unsigned char ULPWUIE:1;
923 unsigned char BCLIE:1;
924 unsigned char EEIE:1;
925 unsigned char C1IE:1;
926 unsigned char C2IE:1;
927 unsigned char OSFIE:1;
930 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
932 #define CCP2IE PIE2_bits.CCP2IE
933 #define ULPWUIE PIE2_bits.ULPWUIE
934 #define BCLIE PIE2_bits.BCLIE
935 #define EEIE PIE2_bits.EEIE
936 #define C1IE PIE2_bits.C1IE
937 #define C2IE PIE2_bits.C2IE
938 #define OSFIE PIE2_bits.OSFIE
940 // ----- PIR1 bits --------------------
943 unsigned char TMR1IF:1;
944 unsigned char TMR2IF:1;
945 unsigned char CCP1IF:1;
946 unsigned char SSPIF:1;
947 unsigned char TXIF:1;
948 unsigned char RCIF:1;
949 unsigned char ADIF:1;
953 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
955 #define TMR1IF PIR1_bits.TMR1IF
956 #define TMR2IF PIR1_bits.TMR2IF
957 #define CCP1IF PIR1_bits.CCP1IF
958 #define SSPIF PIR1_bits.SSPIF
959 #define TXIF PIR1_bits.TXIF
960 #define RCIF PIR1_bits.RCIF
961 #define ADIF PIR1_bits.ADIF
963 // ----- PIR2 bits --------------------
966 unsigned char CCP2IF:1;
968 unsigned char ULPWUIF:1;
969 unsigned char BCLIF:1;
970 unsigned char EEIF:1;
971 unsigned char C1IF:1;
972 unsigned char C2IF:1;
973 unsigned char OSPIF:1;
976 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
978 #define CCP2IF PIR2_bits.CCP2IF
979 #define ULPWUIF PIR2_bits.ULPWUIF
980 #define BCLIF PIR2_bits.BCLIF
981 #define EEIF PIR2_bits.EEIF
982 #define C1IF PIR2_bits.C1IF
983 #define C2IF PIR2_bits.C2IF
984 #define OSPIF PIR2_bits.OSPIF
986 // ----- PORTA bits --------------------
999 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
1001 #define RA0 PORTA_bits.RA0
1002 #define RA1 PORTA_bits.RA1
1003 #define RA2 PORTA_bits.RA2
1004 #define RA3 PORTA_bits.RA3
1005 #define RA4 PORTA_bits.RA4
1006 #define RA5 PORTA_bits.RA5
1008 // ----- PORTB bits --------------------
1011 unsigned char RB0:1;
1012 unsigned char RB1:1;
1013 unsigned char RB2:1;
1014 unsigned char RB3:1;
1015 unsigned char RB4:1;
1016 unsigned char RB5:1;
1017 unsigned char RB6:1;
1018 unsigned char RB7:1;
1021 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
1023 #define RB0 PORTB_bits.RB0
1024 #define RB1 PORTB_bits.RB1
1025 #define RB2 PORTB_bits.RB2
1026 #define RB3 PORTB_bits.RB3
1027 #define RB4 PORTB_bits.RB4
1028 #define RB5 PORTB_bits.RB5
1029 #define RB6 PORTB_bits.RB6
1030 #define RB7 PORTB_bits.RB7
1032 // ----- PORTC bits --------------------
1035 unsigned char RC0:1;
1036 unsigned char RC1:1;
1037 unsigned char RC2:1;
1038 unsigned char RC3:1;
1039 unsigned char RC4:1;
1040 unsigned char RC5:1;
1041 unsigned char RC6:1;
1042 unsigned char RC7:1;
1045 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
1047 #define RC0 PORTC_bits.RC0
1048 #define RC1 PORTC_bits.RC1
1049 #define RC2 PORTC_bits.RC2
1050 #define RC3 PORTC_bits.RC3
1051 #define RC4 PORTC_bits.RC4
1052 #define RC5 PORTC_bits.RC5
1053 #define RC6 PORTC_bits.RC6
1054 #define RC7 PORTC_bits.RC7
1056 // ----- PORTE bits --------------------
1059 unsigned char RE0:1;
1060 unsigned char RE1:1;
1061 unsigned char RE2:1;
1069 extern volatile __PORTE_bits_t __at(PORTE_ADDR) PORTE_bits;
1071 #define RE0 PORTE_bits.RE0
1072 #define RE1 PORTE_bits.RE1
1073 #define RE2 PORTE_bits.RE2
1075 // ----- PSTRCON bits --------------------
1078 unsigned char STRA:1;
1079 unsigned char STRB:1;
1080 unsigned char STRC:1;
1081 unsigned char STRD:1;
1082 unsigned char STRSYNC:1;
1088 extern volatile __PSTRCON_bits_t __at(PSTRCON_ADDR) PSTRCON_bits;
1090 #define STRA PSTRCON_bits.STRA
1091 #define STRB PSTRCON_bits.STRB
1092 #define STRC PSTRCON_bits.STRC
1093 #define STRD PSTRCON_bits.STRD
1094 #define STRSYNC PSTRCON_bits.STRSYNC
1096 // ----- PWM1CON bits --------------------
1099 unsigned char PDC0:1;
1100 unsigned char PDC1:1;
1101 unsigned char PDC2:1;
1102 unsigned char PDC3:1;
1103 unsigned char PDC4:1;
1104 unsigned char PDC5:1;
1105 unsigned char PDC6:1;
1106 unsigned char PRSEN:1;
1109 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
1111 #define PDC0 PWM1CON_bits.PDC0
1112 #define PDC1 PWM1CON_bits.PDC1
1113 #define PDC2 PWM1CON_bits.PDC2
1114 #define PDC3 PWM1CON_bits.PDC3
1115 #define PDC4 PWM1CON_bits.PDC4
1116 #define PDC5 PWM1CON_bits.PDC5
1117 #define PDC6 PWM1CON_bits.PDC6
1118 #define PRSEN PWM1CON_bits.PRSEN
1120 // ----- RCSTA bits --------------------
1123 unsigned char RX9D:1;
1124 unsigned char OERR:1;
1125 unsigned char FERR:1;
1126 unsigned char ADDEN:1;
1127 unsigned char CREN:1;
1128 unsigned char SREN:1;
1129 unsigned char RX9:1;
1130 unsigned char SPEN:1;
1133 unsigned char RCD8:1;
1139 unsigned char RC9:1;
1149 unsigned char NOT_RC8:1;
1159 unsigned char RC8_9:1;
1163 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
1165 #define RX9D RCSTA_bits.RX9D
1166 #define RCD8 RCSTA_bits.RCD8
1167 #define OERR RCSTA_bits.OERR
1168 #define FERR RCSTA_bits.FERR
1169 #define ADDEN RCSTA_bits.ADDEN
1170 #define CREN RCSTA_bits.CREN
1171 #define SREN RCSTA_bits.SREN
1172 #define RX9 RCSTA_bits.RX9
1173 #define RC9 RCSTA_bits.RC9
1174 #define NOT_RC8 RCSTA_bits.NOT_RC8
1175 #define RC8_9 RCSTA_bits.RC8_9
1176 #define SPEN RCSTA_bits.SPEN
1178 // ----- SPBRG bits --------------------
1181 unsigned char BRG0:1;
1182 unsigned char BRG1:1;
1183 unsigned char BRG2:1;
1184 unsigned char BRG3:1;
1185 unsigned char BRG4:1;
1186 unsigned char BRG5:1;
1187 unsigned char BRG6:1;
1188 unsigned char BRG7:1;
1191 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
1193 #define BRG0 SPBRG_bits.BRG0
1194 #define BRG1 SPBRG_bits.BRG1
1195 #define BRG2 SPBRG_bits.BRG2
1196 #define BRG3 SPBRG_bits.BRG3
1197 #define BRG4 SPBRG_bits.BRG4
1198 #define BRG5 SPBRG_bits.BRG5
1199 #define BRG6 SPBRG_bits.BRG6
1200 #define BRG7 SPBRG_bits.BRG7
1202 // ----- SPBRGH bits --------------------
1205 unsigned char BRG8:1;
1206 unsigned char BRG9:1;
1207 unsigned char BRG10:1;
1208 unsigned char BRG11:1;
1209 unsigned char BRG12:1;
1210 unsigned char BRG13:1;
1211 unsigned char BRG14:1;
1212 unsigned char BRG15:1;
1215 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
1217 #define BRG8 SPBRGH_bits.BRG8
1218 #define BRG9 SPBRGH_bits.BRG9
1219 #define BRG10 SPBRGH_bits.BRG10
1220 #define BRG11 SPBRGH_bits.BRG11
1221 #define BRG12 SPBRGH_bits.BRG12
1222 #define BRG13 SPBRGH_bits.BRG13
1223 #define BRG14 SPBRGH_bits.BRG14
1224 #define BRG15 SPBRGH_bits.BRG15
1226 // ----- SRCON bits --------------------
1229 unsigned char FVREN:1;
1231 unsigned char PULSR:1;
1232 unsigned char PULSS:1;
1233 unsigned char C2REN:1;
1234 unsigned char C1SEN:1;
1235 unsigned char SR0:1;
1236 unsigned char SR1:1;
1239 extern volatile __SRCON_bits_t __at(SRCON_ADDR) SRCON_bits;
1241 #define FVREN SRCON_bits.FVREN
1242 #define PULSR SRCON_bits.PULSR
1243 #define PULSS SRCON_bits.PULSS
1244 #define C2REN SRCON_bits.C2REN
1245 #define C1SEN SRCON_bits.C1SEN
1246 #define SR0 SRCON_bits.SR0
1247 #define SR1 SRCON_bits.SR1
1249 // ----- SSPCON bits --------------------
1252 unsigned char SSPM0:1;
1253 unsigned char SSPM1:1;
1254 unsigned char SSPM2:1;
1255 unsigned char SSPM3:1;
1256 unsigned char CKP:1;
1257 unsigned char SSPEN:1;
1258 unsigned char SSPOV:1;
1259 unsigned char WCOL:1;
1262 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1264 #define SSPM0 SSPCON_bits.SSPM0
1265 #define SSPM1 SSPCON_bits.SSPM1
1266 #define SSPM2 SSPCON_bits.SSPM2
1267 #define SSPM3 SSPCON_bits.SSPM3
1268 #define CKP SSPCON_bits.CKP
1269 #define SSPEN SSPCON_bits.SSPEN
1270 #define SSPOV SSPCON_bits.SSPOV
1271 #define WCOL SSPCON_bits.WCOL
1273 // ----- SSPCON2 bits --------------------
1276 unsigned char SEN:1;
1277 unsigned char RSEN:1;
1278 unsigned char PEN:1;
1279 unsigned char RCEN:1;
1280 unsigned char ACKEN:1;
1281 unsigned char ACKDT:1;
1282 unsigned char ACKSTAT:1;
1283 unsigned char GCEN:1;
1286 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
1288 #define SEN SSPCON2_bits.SEN
1289 #define RSEN SSPCON2_bits.RSEN
1290 #define PEN SSPCON2_bits.PEN
1291 #define RCEN SSPCON2_bits.RCEN
1292 #define ACKEN SSPCON2_bits.ACKEN
1293 #define ACKDT SSPCON2_bits.ACKDT
1294 #define ACKSTAT SSPCON2_bits.ACKSTAT
1295 #define GCEN SSPCON2_bits.GCEN
1297 // ----- SSPSTAT bits --------------------
1306 unsigned char CKE:1;
1307 unsigned char SMP:1;
1312 unsigned char I2C_READ:1;
1313 unsigned char I2C_START:1;
1314 unsigned char I2C_STOP:1;
1315 unsigned char I2C_DATA:1;
1322 unsigned char NOT_W:1;
1325 unsigned char NOT_A:1;
1332 unsigned char NOT_WRITE:1;
1335 unsigned char NOT_ADDRESS:1;
1342 unsigned char R_W:1;
1345 unsigned char D_A:1;
1352 unsigned char READ_WRITE:1;
1355 unsigned char DATA_ADDRESS:1;
1360 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1362 #define BF SSPSTAT_bits.BF
1363 #define UA SSPSTAT_bits.UA
1364 #define R SSPSTAT_bits.R
1365 #define I2C_READ SSPSTAT_bits.I2C_READ
1366 #define NOT_W SSPSTAT_bits.NOT_W
1367 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1368 #define R_W SSPSTAT_bits.R_W
1369 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1370 #define S SSPSTAT_bits.S
1371 #define I2C_START SSPSTAT_bits.I2C_START
1372 #define P SSPSTAT_bits.P
1373 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1374 #define D SSPSTAT_bits.D
1375 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1376 #define NOT_A SSPSTAT_bits.NOT_A
1377 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1378 #define D_A SSPSTAT_bits.D_A
1379 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1380 #define CKE SSPSTAT_bits.CKE
1381 #define SMP SSPSTAT_bits.SMP
1383 // ----- STATUS bits --------------------
1389 unsigned char NOT_PD:1;
1390 unsigned char NOT_TO:1;
1391 unsigned char RP0:1;
1392 unsigned char RP1:1;
1393 unsigned char IRP:1;
1396 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1398 #define C STATUS_bits.C
1399 #define DC STATUS_bits.DC
1400 #define Z STATUS_bits.Z
1401 #define NOT_PD STATUS_bits.NOT_PD
1402 #define NOT_TO STATUS_bits.NOT_TO
1403 #define RP0 STATUS_bits.RP0
1404 #define RP1 STATUS_bits.RP1
1405 #define IRP STATUS_bits.IRP
1407 // ----- T1CON bits --------------------
1410 unsigned char TMR1ON:1;
1411 unsigned char TMR1CS:1;
1412 unsigned char NOT_T1SYNC:1;
1413 unsigned char T1OSCEN:1;
1414 unsigned char T1CKPS0:1;
1415 unsigned char T1CKPS1:1;
1422 unsigned char T1INSYNC:1;
1432 unsigned char T1SYNC:1;
1440 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1442 #define TMR1ON T1CON_bits.TMR1ON
1443 #define TMR1CS T1CON_bits.TMR1CS
1444 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1445 #define T1INSYNC T1CON_bits.T1INSYNC
1446 #define T1SYNC T1CON_bits.T1SYNC
1447 #define T1OSCEN T1CON_bits.T1OSCEN
1448 #define T1CKPS0 T1CON_bits.T1CKPS0
1449 #define T1CKPS1 T1CON_bits.T1CKPS1
1451 // ----- T2CON bits --------------------
1454 unsigned char T2CKPS0:1;
1455 unsigned char T2CKPS1:1;
1456 unsigned char TMR2ON:1;
1457 unsigned char TOUTPS0:1;
1458 unsigned char TOUTPS1:1;
1459 unsigned char TOUTPS2:1;
1460 unsigned char TOUTPS3:1;
1464 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1466 #define T2CKPS0 T2CON_bits.T2CKPS0
1467 #define T2CKPS1 T2CON_bits.T2CKPS1
1468 #define TMR2ON T2CON_bits.TMR2ON
1469 #define TOUTPS0 T2CON_bits.TOUTPS0
1470 #define TOUTPS1 T2CON_bits.TOUTPS1
1471 #define TOUTPS2 T2CON_bits.TOUTPS2
1472 #define TOUTPS3 T2CON_bits.TOUTPS3
1474 // ----- TRISA bits --------------------
1477 unsigned char TRISA0:1;
1478 unsigned char TRISA1:1;
1479 unsigned char TRISA2:1;
1480 unsigned char TRISA3:1;
1481 unsigned char TRISA4:1;
1482 unsigned char TRISA5:1;
1487 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1489 #define TRISA0 TRISA_bits.TRISA0
1490 #define TRISA1 TRISA_bits.TRISA1
1491 #define TRISA2 TRISA_bits.TRISA2
1492 #define TRISA3 TRISA_bits.TRISA3
1493 #define TRISA4 TRISA_bits.TRISA4
1494 #define TRISA5 TRISA_bits.TRISA5
1496 // ----- TRISB bits --------------------
1499 unsigned char TRISB0:1;
1500 unsigned char TRISB1:1;
1501 unsigned char TRISB2:1;
1502 unsigned char TRISB3:1;
1503 unsigned char TRISB4:1;
1504 unsigned char TRISB5:1;
1505 unsigned char TRISB6:1;
1506 unsigned char TRISB7:1;
1509 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1511 #define TRISB0 TRISB_bits.TRISB0
1512 #define TRISB1 TRISB_bits.TRISB1
1513 #define TRISB2 TRISB_bits.TRISB2
1514 #define TRISB3 TRISB_bits.TRISB3
1515 #define TRISB4 TRISB_bits.TRISB4
1516 #define TRISB5 TRISB_bits.TRISB5
1517 #define TRISB6 TRISB_bits.TRISB6
1518 #define TRISB7 TRISB_bits.TRISB7
1520 // ----- TRISC bits --------------------
1523 unsigned char TRISC0:1;
1524 unsigned char TRISC1:1;
1525 unsigned char TRISC2:1;
1526 unsigned char TRISC3:1;
1527 unsigned char TRISC4:1;
1528 unsigned char TRISC5:1;
1529 unsigned char TRISC6:1;
1530 unsigned char TRISC7:1;
1533 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1535 #define TRISC0 TRISC_bits.TRISC0
1536 #define TRISC1 TRISC_bits.TRISC1
1537 #define TRISC2 TRISC_bits.TRISC2
1538 #define TRISC3 TRISC_bits.TRISC3
1539 #define TRISC4 TRISC_bits.TRISC4
1540 #define TRISC5 TRISC_bits.TRISC5
1541 #define TRISC6 TRISC_bits.TRISC6
1542 #define TRISC7 TRISC_bits.TRISC7
1544 // ----- TRISE bits --------------------
1547 unsigned char TRISE0:1;
1548 unsigned char TRISE1:1;
1549 unsigned char TRISE2:1;
1557 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1559 #define TRISE0 TRISE_bits.TRISE0
1560 #define TRISE1 TRISE_bits.TRISE1
1561 #define TRISE2 TRISE_bits.TRISE2
1563 // ----- TXSTA bits --------------------
1566 unsigned char TX9D:1;
1567 unsigned char TRMT:1;
1568 unsigned char BRGH:1;
1570 unsigned char SYNC:1;
1571 unsigned char TXEN:1;
1572 unsigned char TX9:1;
1573 unsigned char CSRC:1;
1576 unsigned char TXD8:1;
1582 unsigned char NOT_TX8:1;
1592 unsigned char TX8_9:1;
1596 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1598 #define TX9D TXSTA_bits.TX9D
1599 #define TXD8 TXSTA_bits.TXD8
1600 #define TRMT TXSTA_bits.TRMT
1601 #define BRGH TXSTA_bits.BRGH
1602 #define SYNC TXSTA_bits.SYNC
1603 #define TXEN TXSTA_bits.TXEN
1604 #define TX9 TXSTA_bits.TX9
1605 #define NOT_TX8 TXSTA_bits.NOT_TX8
1606 #define TX8_9 TXSTA_bits.TX8_9
1607 #define CSRC TXSTA_bits.CSRC
1609 // ----- VRCON bits --------------------
1612 unsigned char VR0:1;
1613 unsigned char VR1:1;
1614 unsigned char VR2:1;
1615 unsigned char VR3:1;
1616 unsigned char VRSS:1;
1617 unsigned char VRR:1;
1618 unsigned char VROE:1;
1619 unsigned char VREN:1;
1622 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1624 #define VR0 VRCON_bits.VR0
1625 #define VR1 VRCON_bits.VR1
1626 #define VR2 VRCON_bits.VR2
1627 #define VR3 VRCON_bits.VR3
1628 #define VRSS VRCON_bits.VRSS
1629 #define VRR VRCON_bits.VRR
1630 #define VROE VRCON_bits.VROE
1631 #define VREN VRCON_bits.VREN
1633 // ----- WDTCON bits --------------------
1636 unsigned char SWDTEN:1;
1637 unsigned char WDTPS0:1;
1638 unsigned char WDTPS1:1;
1639 unsigned char WDTPS2:1;
1640 unsigned char WDTPS3:1;
1646 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1648 #define SWDTEN WDTCON_bits.SWDTEN
1649 #define WDTPS0 WDTCON_bits.WDTPS0
1650 #define WDTPS1 WDTCON_bits.WDTPS1
1651 #define WDTPS2 WDTCON_bits.WDTPS2
1652 #define WDTPS3 WDTCON_bits.WDTPS3
1654 // ----- WPUB bits --------------------
1657 unsigned char WPUB0:1;
1658 unsigned char WPUB1:1;
1659 unsigned char WPUB2:1;
1660 unsigned char WPUB3:1;
1661 unsigned char WPUB4:1;
1662 unsigned char WPUB5:1;
1663 unsigned char WPUB6:1;
1664 unsigned char WPUB7:1;
1667 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1669 #define WPUB0 WPUB_bits.WPUB0
1670 #define WPUB1 WPUB_bits.WPUB1
1671 #define WPUB2 WPUB_bits.WPUB2
1672 #define WPUB3 WPUB_bits.WPUB3
1673 #define WPUB4 WPUB_bits.WPUB4
1674 #define WPUB5 WPUB_bits.WPUB5
1675 #define WPUB6 WPUB_bits.WPUB6
1676 #define WPUB7 WPUB_bits.WPUB7