2 // Register Declarations for Microchip 16F876A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRESH_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define SSPCON2_ADDR 0x0091
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define SSPSTAT_ADDR 0x0094
69 #define TXSTA_ADDR 0x0098
70 #define SPBRG_ADDR 0x0099
71 #define CMCON_ADDR 0x009C
72 #define CVRCON_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
75 #define EEDATA_ADDR 0x010C
76 #define EEADR_ADDR 0x010D
77 #define EEDATH_ADDR 0x010E
78 #define EEADRH_ADDR 0x010F
79 #define EECON1_ADDR 0x018C
80 #define EECON2_ADDR 0x018D
83 // Memory organization.
89 // P16F876A.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
92 // This header file defines configurations, registers, and other useful bits of
93 // information for the PIC16F877A microcontroller. These names are taken to match
94 // the data sheets as closely as possible.
96 // Note that the processor must be selected before this file is
97 // included. The processor may be selected the following ways:
99 // 1. Command line switch:
100 // C:\ MPASM MYFILE.ASM /PIC16F876A
101 // 2. LIST directive in the source file
103 // 3. Processor Type entry in the MPASM full-screen interface
105 //==========================================================================
109 //==========================================================================
112 //1.03 11/17/05 Added the INTCON bits TMR0IE and TMR0IF and the ADCON1 bit ADCS2.
113 //1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section.
114 //1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE
115 //1.00 04/19/01 Initial Release (BD - generated from PIC16F877.inc)
117 //==========================================================================
121 //==========================================================================
124 // MESSG "Processor-header file mismatch. Verify selected processor."
127 //==========================================================================
129 // Register Definitions
131 //==========================================================================
136 //----- Register Files------------------------------------------------------
138 extern __sfr __at (INDF_ADDR) INDF;
139 extern __sfr __at (TMR0_ADDR) TMR0;
140 extern __sfr __at (PCL_ADDR) PCL;
141 extern __sfr __at (STATUS_ADDR) STATUS;
142 extern __sfr __at (FSR_ADDR) FSR;
143 extern __sfr __at (PORTA_ADDR) PORTA;
144 extern __sfr __at (PORTB_ADDR) PORTB;
145 extern __sfr __at (PORTC_ADDR) PORTC;
146 extern __sfr __at (PCLATH_ADDR) PCLATH;
147 extern __sfr __at (INTCON_ADDR) INTCON;
148 extern __sfr __at (PIR1_ADDR) PIR1;
149 extern __sfr __at (PIR2_ADDR) PIR2;
150 extern __sfr __at (TMR1L_ADDR) TMR1L;
151 extern __sfr __at (TMR1H_ADDR) TMR1H;
152 extern __sfr __at (T1CON_ADDR) T1CON;
153 extern __sfr __at (TMR2_ADDR) TMR2;
154 extern __sfr __at (T2CON_ADDR) T2CON;
155 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
156 extern __sfr __at (SSPCON_ADDR) SSPCON;
157 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
158 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
159 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
160 extern __sfr __at (RCSTA_ADDR) RCSTA;
161 extern __sfr __at (TXREG_ADDR) TXREG;
162 extern __sfr __at (RCREG_ADDR) RCREG;
163 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
164 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
165 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
166 extern __sfr __at (ADRESH_ADDR) ADRESH;
167 extern __sfr __at (ADCON0_ADDR) ADCON0;
169 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
170 extern __sfr __at (TRISA_ADDR) TRISA;
171 extern __sfr __at (TRISB_ADDR) TRISB;
172 extern __sfr __at (TRISC_ADDR) TRISC;
173 extern __sfr __at (PIE1_ADDR) PIE1;
174 extern __sfr __at (PIE2_ADDR) PIE2;
175 extern __sfr __at (PCON_ADDR) PCON;
176 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
177 extern __sfr __at (PR2_ADDR) PR2;
178 extern __sfr __at (SSPADD_ADDR) SSPADD;
179 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
180 extern __sfr __at (TXSTA_ADDR) TXSTA;
181 extern __sfr __at (SPBRG_ADDR) SPBRG;
182 extern __sfr __at (CMCON_ADDR) CMCON;
183 extern __sfr __at (CVRCON_ADDR) CVRCON;
184 extern __sfr __at (ADRESL_ADDR) ADRESL;
185 extern __sfr __at (ADCON1_ADDR) ADCON1;
187 extern __sfr __at (EEDATA_ADDR) EEDATA;
188 extern __sfr __at (EEADR_ADDR) EEADR;
189 extern __sfr __at (EEDATH_ADDR) EEDATH;
190 extern __sfr __at (EEADRH_ADDR) EEADRH;
192 extern __sfr __at (EECON1_ADDR) EECON1;
193 extern __sfr __at (EECON2_ADDR) EECON2;
195 //----- STATUS Bits --------------------------------------------------------
198 //----- INTCON Bits --------------------------------------------------------
201 //----- PIR1 Bits ----------------------------------------------------------
204 //----- PIR2 Bits ----------------------------------------------------------
207 //----- T1CON Bits ---------------------------------------------------------
210 //----- T2CON Bits ---------------------------------------------------------
213 //----- SSPCON Bits --------------------------------------------------------
216 //----- CCP1CON Bits -------------------------------------------------------
219 //----- RCSTA Bits ---------------------------------------------------------
222 //----- CCP2CON Bits -------------------------------------------------------
225 //----- ADCON0 Bits --------------------------------------------------------
228 //----- OPTION_REG Bits -----------------------------------------------------
231 //----- PIE1 Bits ----------------------------------------------------------
234 //----- PIE2 Bits ----------------------------------------------------------
237 //----- PCON Bits ----------------------------------------------------------
240 //----- SSPCON2 Bits --------------------------------------------------------
243 //----- SSPSTAT Bits -------------------------------------------------------
246 //----- TXSTA Bits ---------------------------------------------------------
250 //----- CMCON Bits ---------------------------------------------------------
252 //----- CVRCON Bits --------------------------------------------------------
254 //----- ADCON1 Bits --------------------------------------------------------
257 //----- EECON1 Bits --------------------------------------------------------
260 //==========================================================================
264 //==========================================================================
267 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B'
268 // __BADRAM H'105', H'107'-H'109'
269 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
271 //==========================================================================
273 // Configuration Bits
275 //==========================================================================
277 #define _CP_ALL 0x1FFF
278 #define _CP_OFF 0x3FFF
279 #define _DEBUG_OFF 0x3FFF
280 #define _DEBUG_ON 0x37FF
281 #define _WRT_OFF 0x3FFF // No prog memmory write protection
282 #define _WRT_256 0x3DFF // First 256 prog memmory write protected
283 #define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected
284 #define _WRT_HALF 0x39FF // First half memmory write protected
285 #define _CPD_OFF 0x3FFF
286 #define _CPD_ON 0x3EFF
287 #define _LVP_ON 0x3FFF
288 #define _LVP_OFF 0x3F7F
289 #define _BODEN_ON 0x3FFF
290 #define _BODEN_OFF 0x3FBF
291 #define _PWRTE_OFF 0x3FFF
292 #define _PWRTE_ON 0x3FF7
293 #define _WDT_ON 0x3FFF
294 #define _WDT_OFF 0x3FFB
295 #define _RC_OSC 0x3FFF
296 #define _HS_OSC 0x3FFE
297 #define _XT_OSC 0x3FFD
298 #define _LP_OSC 0x3FFC
302 // ----- ADCON0 bits --------------------
305 unsigned char ADON:1;
308 unsigned char CHS0:1;
309 unsigned char CHS1:1;
310 unsigned char CHS2:1;
311 unsigned char ADCS0:1;
312 unsigned char ADCS1:1;
317 unsigned char NOT_DONE:1;
327 unsigned char GO_DONE:1;
335 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
337 #define ADON ADCON0_bits.ADON
338 #define GO ADCON0_bits.GO
339 #define NOT_DONE ADCON0_bits.NOT_DONE
340 #define GO_DONE ADCON0_bits.GO_DONE
341 #define CHS0 ADCON0_bits.CHS0
342 #define CHS1 ADCON0_bits.CHS1
343 #define CHS2 ADCON0_bits.CHS2
344 #define ADCS0 ADCON0_bits.ADCS0
345 #define ADCS1 ADCON0_bits.ADCS1
347 // ----- ADCON1 bits --------------------
350 unsigned char PCFG0:1;
351 unsigned char PCFG1:1;
352 unsigned char PCFG2:1;
353 unsigned char PCFG3:1;
356 unsigned char ADCS2:1;
357 unsigned char ADFM:1;
360 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
362 #define PCFG0 ADCON1_bits.PCFG0
363 #define PCFG1 ADCON1_bits.PCFG1
364 #define PCFG2 ADCON1_bits.PCFG2
365 #define PCFG3 ADCON1_bits.PCFG3
366 #define ADCS2 ADCON1_bits.ADCS2
367 #define ADFM ADCON1_bits.ADFM
369 // ----- CCP1CON bits --------------------
372 unsigned char CCP1M0:1;
373 unsigned char CCP1M1:1;
374 unsigned char CCP1M2:1;
375 unsigned char CCP1M3:1;
376 unsigned char CCP1Y:1;
377 unsigned char CCP1X:1;
382 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
384 #define CCP1M0 CCP1CON_bits.CCP1M0
385 #define CCP1M1 CCP1CON_bits.CCP1M1
386 #define CCP1M2 CCP1CON_bits.CCP1M2
387 #define CCP1M3 CCP1CON_bits.CCP1M3
388 #define CCP1Y CCP1CON_bits.CCP1Y
389 #define CCP1X CCP1CON_bits.CCP1X
391 // ----- CCP2CON bits --------------------
394 unsigned char CCP2M0:1;
395 unsigned char CCP2M1:1;
396 unsigned char CCP2M2:1;
397 unsigned char CCP2M3:1;
398 unsigned char CCP2Y:1;
399 unsigned char CCP2X:1;
404 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
406 #define CCP2M0 CCP2CON_bits.CCP2M0
407 #define CCP2M1 CCP2CON_bits.CCP2M1
408 #define CCP2M2 CCP2CON_bits.CCP2M2
409 #define CCP2M3 CCP2CON_bits.CCP2M3
410 #define CCP2Y CCP2CON_bits.CCP2Y
411 #define CCP2X CCP2CON_bits.CCP2X
413 // ----- CMCON bits --------------------
420 unsigned char C1INV:1;
421 unsigned char C2INV:1;
422 unsigned char C1OUT:1;
423 unsigned char C2OUT:1;
426 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
428 #define CM0 CMCON_bits.CM0
429 #define CM1 CMCON_bits.CM1
430 #define CM2 CMCON_bits.CM2
431 #define CIS CMCON_bits.CIS
432 #define C1INV CMCON_bits.C1INV
433 #define C2INV CMCON_bits.C2INV
434 #define C1OUT CMCON_bits.C1OUT
435 #define C2OUT CMCON_bits.C2OUT
437 // ----- CVRCON bits --------------------
440 unsigned char CVR0:1;
441 unsigned char CVR1:1;
442 unsigned char CVR2:1;
443 unsigned char CVR3:1;
445 unsigned char CVRR:1;
446 unsigned char CVROE:1;
447 unsigned char CVREN:1;
450 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
452 #define CVR0 CVRCON_bits.CVR0
453 #define CVR1 CVRCON_bits.CVR1
454 #define CVR2 CVRCON_bits.CVR2
455 #define CVR3 CVRCON_bits.CVR3
456 #define CVRR CVRCON_bits.CVRR
457 #define CVROE CVRCON_bits.CVROE
458 #define CVREN CVRCON_bits.CVREN
460 // ----- EECON1 bits --------------------
465 unsigned char WREN:1;
466 unsigned char WRERR:1;
470 unsigned char EEPGD:1;
473 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
475 #define RD EECON1_bits.RD
476 #define WR EECON1_bits.WR
477 #define WREN EECON1_bits.WREN
478 #define WRERR EECON1_bits.WRERR
479 #define EEPGD EECON1_bits.EEPGD
481 // ----- INTCON bits --------------------
484 unsigned char RBIF:1;
485 unsigned char INTF:1;
486 unsigned char T0IF:1;
487 unsigned char RBIE:1;
488 unsigned char INTE:1;
489 unsigned char T0IE:1;
490 unsigned char PEIE:1;
496 unsigned char TMR0IF:1;
499 unsigned char TMR0IE:1;
504 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
506 #define RBIF INTCON_bits.RBIF
507 #define INTF INTCON_bits.INTF
508 #define T0IF INTCON_bits.T0IF
509 #define TMR0IF INTCON_bits.TMR0IF
510 #define RBIE INTCON_bits.RBIE
511 #define INTE INTCON_bits.INTE
512 #define T0IE INTCON_bits.T0IE
513 #define TMR0IE INTCON_bits.TMR0IE
514 #define PEIE INTCON_bits.PEIE
515 #define GIE INTCON_bits.GIE
517 // ----- OPTION_REG bits --------------------
524 unsigned char T0SE:1;
525 unsigned char T0CS:1;
526 unsigned char INTEDG:1;
527 unsigned char NOT_RBPU:1;
529 } __OPTION_REG_bits_t;
530 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
532 #define PS0 OPTION_REG_bits.PS0
533 #define PS1 OPTION_REG_bits.PS1
534 #define PS2 OPTION_REG_bits.PS2
535 #define PSA OPTION_REG_bits.PSA
536 #define T0SE OPTION_REG_bits.T0SE
537 #define T0CS OPTION_REG_bits.T0CS
538 #define INTEDG OPTION_REG_bits.INTEDG
539 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
541 // ----- PCON bits --------------------
544 unsigned char NOT_BO:1;
545 unsigned char NOT_POR:1;
554 unsigned char NOT_BOR:1;
564 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
566 #define NOT_BO PCON_bits.NOT_BO
567 #define NOT_BOR PCON_bits.NOT_BOR
568 #define NOT_POR PCON_bits.NOT_POR
570 // ----- PIE1 bits --------------------
573 unsigned char TMR1IE:1;
574 unsigned char TMR2IE:1;
575 unsigned char CCP1IE:1;
576 unsigned char SSPIE:1;
577 unsigned char TXIE:1;
578 unsigned char RCIE:1;
579 unsigned char ADIE:1;
583 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
585 #define TMR1IE PIE1_bits.TMR1IE
586 #define TMR2IE PIE1_bits.TMR2IE
587 #define CCP1IE PIE1_bits.CCP1IE
588 #define SSPIE PIE1_bits.SSPIE
589 #define TXIE PIE1_bits.TXIE
590 #define RCIE PIE1_bits.RCIE
591 #define ADIE PIE1_bits.ADIE
593 // ----- PIE2 bits --------------------
596 unsigned char CCP2IE:1;
599 unsigned char BCLIE:1;
600 unsigned char EEIE:1;
602 unsigned char CMIE:1;
606 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
608 #define CCP2IE PIE2_bits.CCP2IE
609 #define BCLIE PIE2_bits.BCLIE
610 #define EEIE PIE2_bits.EEIE
611 #define CMIE PIE2_bits.CMIE
613 // ----- PIR1 bits --------------------
616 unsigned char TMR1IF:1;
617 unsigned char TMR2IF:1;
618 unsigned char CCP1IF:1;
619 unsigned char SSPIF:1;
620 unsigned char TXIF:1;
621 unsigned char RCIF:1;
622 unsigned char ADIF:1;
626 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
628 #define TMR1IF PIR1_bits.TMR1IF
629 #define TMR2IF PIR1_bits.TMR2IF
630 #define CCP1IF PIR1_bits.CCP1IF
631 #define SSPIF PIR1_bits.SSPIF
632 #define TXIF PIR1_bits.TXIF
633 #define RCIF PIR1_bits.RCIF
634 #define ADIF PIR1_bits.ADIF
636 // ----- PIR2 bits --------------------
639 unsigned char CCP2IF:1;
642 unsigned char BCLIF:1;
643 unsigned char EEIF:1;
645 unsigned char CMIF:1;
649 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
651 #define CCP2IF PIR2_bits.CCP2IF
652 #define BCLIF PIR2_bits.BCLIF
653 #define EEIF PIR2_bits.EEIF
654 #define CMIF PIR2_bits.CMIF
656 // ----- PORTA bits --------------------
669 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
671 #define RA0 PORTA_bits.RA0
672 #define RA1 PORTA_bits.RA1
673 #define RA2 PORTA_bits.RA2
674 #define RA3 PORTA_bits.RA3
675 #define RA4 PORTA_bits.RA4
676 #define RA5 PORTA_bits.RA5
678 // ----- PORTB bits --------------------
691 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
693 #define RB0 PORTB_bits.RB0
694 #define RB1 PORTB_bits.RB1
695 #define RB2 PORTB_bits.RB2
696 #define RB3 PORTB_bits.RB3
697 #define RB4 PORTB_bits.RB4
698 #define RB5 PORTB_bits.RB5
699 #define RB6 PORTB_bits.RB6
700 #define RB7 PORTB_bits.RB7
702 // ----- PORTC bits --------------------
715 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
717 #define RC0 PORTC_bits.RC0
718 #define RC1 PORTC_bits.RC1
719 #define RC2 PORTC_bits.RC2
720 #define RC3 PORTC_bits.RC3
721 #define RC4 PORTC_bits.RC4
722 #define RC5 PORTC_bits.RC5
723 #define RC6 PORTC_bits.RC6
724 #define RC7 PORTC_bits.RC7
726 // ----- RCSTA bits --------------------
729 unsigned char RX9D:1;
730 unsigned char OERR:1;
731 unsigned char FERR:1;
732 unsigned char ADDEN:1;
733 unsigned char CREN:1;
734 unsigned char SREN:1;
736 unsigned char SPEN:1;
739 unsigned char RCD8:1;
755 unsigned char NOT_RC8:1;
765 unsigned char RC8_9:1;
769 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
771 #define RX9D RCSTA_bits.RX9D
772 #define RCD8 RCSTA_bits.RCD8
773 #define OERR RCSTA_bits.OERR
774 #define FERR RCSTA_bits.FERR
775 #define ADDEN RCSTA_bits.ADDEN
776 #define CREN RCSTA_bits.CREN
777 #define SREN RCSTA_bits.SREN
778 #define RX9 RCSTA_bits.RX9
779 #define RC9 RCSTA_bits.RC9
780 #define NOT_RC8 RCSTA_bits.NOT_RC8
781 #define RC8_9 RCSTA_bits.RC8_9
782 #define SPEN RCSTA_bits.SPEN
784 // ----- SSPCON bits --------------------
787 unsigned char SSPM0:1;
788 unsigned char SSPM1:1;
789 unsigned char SSPM2:1;
790 unsigned char SSPM3:1;
792 unsigned char SSPEN:1;
793 unsigned char SSPOV:1;
794 unsigned char WCOL:1;
797 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
799 #define SSPM0 SSPCON_bits.SSPM0
800 #define SSPM1 SSPCON_bits.SSPM1
801 #define SSPM2 SSPCON_bits.SSPM2
802 #define SSPM3 SSPCON_bits.SSPM3
803 #define CKP SSPCON_bits.CKP
804 #define SSPEN SSPCON_bits.SSPEN
805 #define SSPOV SSPCON_bits.SSPOV
806 #define WCOL SSPCON_bits.WCOL
808 // ----- SSPCON2 bits --------------------
812 unsigned char RSEN:1;
814 unsigned char RCEN:1;
815 unsigned char ACKEN:1;
816 unsigned char ACKDT:1;
817 unsigned char ACKSTAT:1;
818 unsigned char GCEN:1;
821 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
823 #define SEN SSPCON2_bits.SEN
824 #define RSEN SSPCON2_bits.RSEN
825 #define PEN SSPCON2_bits.PEN
826 #define RCEN SSPCON2_bits.RCEN
827 #define ACKEN SSPCON2_bits.ACKEN
828 #define ACKDT SSPCON2_bits.ACKDT
829 #define ACKSTAT SSPCON2_bits.ACKSTAT
830 #define GCEN SSPCON2_bits.GCEN
832 // ----- SSPSTAT bits --------------------
847 unsigned char I2C_READ:1;
848 unsigned char I2C_START:1;
849 unsigned char I2C_STOP:1;
850 unsigned char I2C_DATA:1;
857 unsigned char NOT_W:1;
860 unsigned char NOT_A:1;
867 unsigned char NOT_WRITE:1;
870 unsigned char NOT_ADDRESS:1;
887 unsigned char READ_WRITE:1;
890 unsigned char DATA_ADDRESS:1;
895 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
897 #define BF SSPSTAT_bits.BF
898 #define UA SSPSTAT_bits.UA
899 #define R SSPSTAT_bits.R
900 #define I2C_READ SSPSTAT_bits.I2C_READ
901 #define NOT_W SSPSTAT_bits.NOT_W
902 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
903 #define R_W SSPSTAT_bits.R_W
904 #define READ_WRITE SSPSTAT_bits.READ_WRITE
905 #define S SSPSTAT_bits.S
906 #define I2C_START SSPSTAT_bits.I2C_START
907 #define P SSPSTAT_bits.P
908 #define I2C_STOP SSPSTAT_bits.I2C_STOP
909 #define D SSPSTAT_bits.D
910 #define I2C_DATA SSPSTAT_bits.I2C_DATA
911 #define NOT_A SSPSTAT_bits.NOT_A
912 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
913 #define D_A SSPSTAT_bits.D_A
914 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
915 #define CKE SSPSTAT_bits.CKE
916 #define SMP SSPSTAT_bits.SMP
918 // ----- STATUS bits --------------------
924 unsigned char NOT_PD:1;
925 unsigned char NOT_TO:1;
931 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
933 #define C STATUS_bits.C
934 #define DC STATUS_bits.DC
935 #define Z STATUS_bits.Z
936 #define NOT_PD STATUS_bits.NOT_PD
937 #define NOT_TO STATUS_bits.NOT_TO
938 #define RP0 STATUS_bits.RP0
939 #define RP1 STATUS_bits.RP1
940 #define IRP STATUS_bits.IRP
942 // ----- T1CON bits --------------------
945 unsigned char TMR1ON:1;
946 unsigned char TMR1CS:1;
947 unsigned char NOT_T1SYNC:1;
948 unsigned char T1OSCEN:1;
949 unsigned char T1CKPS0:1;
950 unsigned char T1CKPS1:1;
957 unsigned char T1INSYNC:1;
967 unsigned char T1SYNC:1;
975 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
977 #define TMR1ON T1CON_bits.TMR1ON
978 #define TMR1CS T1CON_bits.TMR1CS
979 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
980 #define T1INSYNC T1CON_bits.T1INSYNC
981 #define T1SYNC T1CON_bits.T1SYNC
982 #define T1OSCEN T1CON_bits.T1OSCEN
983 #define T1CKPS0 T1CON_bits.T1CKPS0
984 #define T1CKPS1 T1CON_bits.T1CKPS1
986 // ----- T2CON bits --------------------
989 unsigned char T2CKPS0:1;
990 unsigned char T2CKPS1:1;
991 unsigned char TMR2ON:1;
992 unsigned char TOUTPS0:1;
993 unsigned char TOUTPS1:1;
994 unsigned char TOUTPS2:1;
995 unsigned char TOUTPS3:1;
999 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1001 #define T2CKPS0 T2CON_bits.T2CKPS0
1002 #define T2CKPS1 T2CON_bits.T2CKPS1
1003 #define TMR2ON T2CON_bits.TMR2ON
1004 #define TOUTPS0 T2CON_bits.TOUTPS0
1005 #define TOUTPS1 T2CON_bits.TOUTPS1
1006 #define TOUTPS2 T2CON_bits.TOUTPS2
1007 #define TOUTPS3 T2CON_bits.TOUTPS3
1009 // ----- TRISA bits --------------------
1012 unsigned char TRISA0:1;
1013 unsigned char TRISA1:1;
1014 unsigned char TRISA2:1;
1015 unsigned char TRISA3:1;
1016 unsigned char TRISA4:1;
1017 unsigned char TRISA5:1;
1022 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1024 #define TRISA0 TRISA_bits.TRISA0
1025 #define TRISA1 TRISA_bits.TRISA1
1026 #define TRISA2 TRISA_bits.TRISA2
1027 #define TRISA3 TRISA_bits.TRISA3
1028 #define TRISA4 TRISA_bits.TRISA4
1029 #define TRISA5 TRISA_bits.TRISA5
1031 // ----- TRISB bits --------------------
1034 unsigned char TRISB0:1;
1035 unsigned char TRISB1:1;
1036 unsigned char TRISB2:1;
1037 unsigned char TRISB3:1;
1038 unsigned char TRISB4:1;
1039 unsigned char TRISB5:1;
1040 unsigned char TRISB6:1;
1041 unsigned char TRISB7:1;
1044 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1046 #define TRISB0 TRISB_bits.TRISB0
1047 #define TRISB1 TRISB_bits.TRISB1
1048 #define TRISB2 TRISB_bits.TRISB2
1049 #define TRISB3 TRISB_bits.TRISB3
1050 #define TRISB4 TRISB_bits.TRISB4
1051 #define TRISB5 TRISB_bits.TRISB5
1052 #define TRISB6 TRISB_bits.TRISB6
1053 #define TRISB7 TRISB_bits.TRISB7
1055 // ----- TRISC bits --------------------
1058 unsigned char TRISC0:1;
1059 unsigned char TRISC1:1;
1060 unsigned char TRISC2:1;
1061 unsigned char TRISC3:1;
1062 unsigned char TRISC4:1;
1063 unsigned char TRISC5:1;
1064 unsigned char TRISC6:1;
1065 unsigned char TRISC7:1;
1068 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1070 #define TRISC0 TRISC_bits.TRISC0
1071 #define TRISC1 TRISC_bits.TRISC1
1072 #define TRISC2 TRISC_bits.TRISC2
1073 #define TRISC3 TRISC_bits.TRISC3
1074 #define TRISC4 TRISC_bits.TRISC4
1075 #define TRISC5 TRISC_bits.TRISC5
1076 #define TRISC6 TRISC_bits.TRISC6
1077 #define TRISC7 TRISC_bits.TRISC7
1079 // ----- TXSTA bits --------------------
1082 unsigned char TX9D:1;
1083 unsigned char TRMT:1;
1084 unsigned char BRGH:1;
1086 unsigned char SYNC:1;
1087 unsigned char TXEN:1;
1088 unsigned char TX9:1;
1089 unsigned char CSRC:1;
1092 unsigned char TXD8:1;
1098 unsigned char NOT_TX8:1;
1108 unsigned char TX8_9:1;
1112 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1114 #define TX9D TXSTA_bits.TX9D
1115 #define TXD8 TXSTA_bits.TXD8
1116 #define TRMT TXSTA_bits.TRMT
1117 #define BRGH TXSTA_bits.BRGH
1118 #define SYNC TXSTA_bits.SYNC
1119 #define TXEN TXSTA_bits.TXEN
1120 #define TX9 TXSTA_bits.TX9
1121 #define NOT_TX8 TXSTA_bits.NOT_TX8
1122 #define TX8_9 TXSTA_bits.TX8_9
1123 #define CSRC TXSTA_bits.CSRC