2 // Register Declarations for Microchip 16F785 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define CCPR1L_ADDR 0x0013
45 #define CCPR1H_ADDR 0x0014
46 #define CCP1CON_ADDR 0x0015
47 #define WDTCON_ADDR 0x0018
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define TRISC_ADDR 0x0087
54 #define PIE1_ADDR 0x008C
55 #define PCON_ADDR 0x008E
56 #define OSCCON_ADDR 0x008F
57 #define OSCTUNE_ADDR 0x0090
58 #define ANSEL_ADDR 0x0091
59 #define ANSEL0_ADDR 0x0091
60 #define PR2_ADDR 0x0092
61 #define ANSEL1_ADDR 0x0093
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define REFCON_ADDR 0x0098
67 #define VRCON_ADDR 0x0099
68 #define EEDAT_ADDR 0x009A
69 #define EEDATA_ADDR 0x009A
70 #define EEADR_ADDR 0x009B
71 #define EECON1_ADDR 0x009C
72 #define EECON2_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
75 #define PWMCON1_ADDR 0x0110
76 #define PWMCON0_ADDR 0x0111
77 #define PWMCLK_ADDR 0x0112
78 #define PWMPH1_ADDR 0x0113
79 #define PWMPH2_ADDR 0x0114
80 #define CM1CON0_ADDR 0x0119
81 #define CM2CON0_ADDR 0x011A
82 #define CM2CON1_ADDR 0x011B
83 #define OPA1CON_ADDR 0x011C
84 #define OPA2CON_ADDR 0x011D
87 // Memory organization.
93 // P16F785.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
96 // This header file defines configurations, registers, and other useful bits of
97 // information for the PIC16F785 microcontroller. These names are taken to match
98 // the data sheets as closely as possible.
100 // Note that the processor must be selected before this file is
101 // included. The processor may be selected the following ways:
103 // 1. Command line switch:
104 // C:\ MPASM MYFILE.ASM /PIC16F785
105 // 2. LIST directive in the source file
107 // 3. Processor Type entry in the MPASM full-screen interface
109 //==========================================================================
113 //==========================================================================
114 //1.00 03/26/04 Original
115 //1.10 07/12/04 Updated for changes to REFCON and VRCON
116 //1.20 08/26/04 Updated for changes from BOD to BOR
117 //1.30 09/23/04 Corrected addresses for OPA1CON and OPA2CON
118 //1.40 10/25/04 Added WPUA3 bit to WPUA register
119 // Deleted OVRLP bit from PWMCON1 register
120 //==========================================================================
124 //==========================================================================
127 // MESSG "Processor-header file mismatch. Verify selected processor."
130 //==========================================================================
132 // Register Definitions
134 //==========================================================================
139 //----- Register Files------------------------------------------------------
141 extern __sfr __at (INDF_ADDR) INDF;
142 extern __sfr __at (TMR0_ADDR) TMR0;
143 extern __sfr __at (PCL_ADDR) PCL;
144 extern __sfr __at (STATUS_ADDR) STATUS;
145 extern __sfr __at (FSR_ADDR) FSR;
146 extern __sfr __at (PORTA_ADDR) PORTA;
147 extern __sfr __at (PORTB_ADDR) PORTB;
148 extern __sfr __at (PORTC_ADDR) PORTC;
150 extern __sfr __at (PCLATH_ADDR) PCLATH;
151 extern __sfr __at (INTCON_ADDR) INTCON;
152 extern __sfr __at (PIR1_ADDR) PIR1;
154 extern __sfr __at (TMR1L_ADDR) TMR1L;
155 extern __sfr __at (TMR1H_ADDR) TMR1H;
156 extern __sfr __at (T1CON_ADDR) T1CON;
157 extern __sfr __at (TMR2_ADDR) TMR2;
158 extern __sfr __at (T2CON_ADDR) T2CON;
159 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
160 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
161 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
163 extern __sfr __at (WDTCON_ADDR) WDTCON;
165 extern __sfr __at (ADRESH_ADDR) ADRESH;
166 extern __sfr __at (ADCON0_ADDR) ADCON0;
169 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
171 extern __sfr __at (TRISA_ADDR) TRISA;
172 extern __sfr __at (TRISB_ADDR) TRISB;
173 extern __sfr __at (TRISC_ADDR) TRISC;
175 extern __sfr __at (PIE1_ADDR) PIE1;
177 extern __sfr __at (PCON_ADDR) PCON;
178 extern __sfr __at (OSCCON_ADDR) OSCCON;
179 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
180 extern __sfr __at (ANSEL_ADDR) ANSEL;
181 extern __sfr __at (ANSEL0_ADDR) ANSEL0;
182 extern __sfr __at (PR2_ADDR) PR2;
183 extern __sfr __at (ANSEL1_ADDR) ANSEL1;
185 extern __sfr __at (WPU_ADDR) WPU;
186 extern __sfr __at (WPUA_ADDR) WPUA;
187 extern __sfr __at (IOC_ADDR) IOC;
188 extern __sfr __at (IOCA_ADDR) IOCA;
190 extern __sfr __at (REFCON_ADDR) REFCON;
191 extern __sfr __at (VRCON_ADDR) VRCON;
192 extern __sfr __at (EEDAT_ADDR) EEDAT;
193 extern __sfr __at (EEDATA_ADDR) EEDATA;
194 extern __sfr __at (EEADR_ADDR) EEADR;
195 extern __sfr __at (EECON1_ADDR) EECON1;
196 extern __sfr __at (EECON2_ADDR) EECON2;
197 extern __sfr __at (ADRESL_ADDR) ADRESL;
198 extern __sfr __at (ADCON1_ADDR) ADCON1;
201 extern __sfr __at (PWMCON1_ADDR) PWMCON1;
202 extern __sfr __at (PWMCON0_ADDR) PWMCON0;
203 extern __sfr __at (PWMCLK_ADDR) PWMCLK;
204 extern __sfr __at (PWMPH1_ADDR) PWMPH1;
205 extern __sfr __at (PWMPH2_ADDR) PWMPH2;
207 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
208 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
209 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
210 extern __sfr __at (OPA1CON_ADDR) OPA1CON;
211 extern __sfr __at (OPA2CON_ADDR) OPA2CON;
213 //----- STATUS Bits --------------------------------------------------------
216 //----- INTCON Bits --------------------------------------------------------
219 //----- PIR1 Bits ----------------------------------------------------------
222 //----- T1CON Bits ---------------------------------------------------------
225 //----- T2CON Bits ---------------------------------------------------------
228 //----- CCP1CON Bits -------------------------------------------------------
231 //----- WDTCON Bits --------------------------------------------------------
234 //----- ADCON0 Bits --------------------------------------------------------
237 //----- OPTION Bits --------------------------------------------------------
240 //----- PIE1 Bits ----------------------------------------------------------
243 //----- PCON Bits ----------------------------------------------------------
246 //----- OSCCON Bits --------------------------------------------------------
249 //----- OSCTUNE Bits -------------------------------------------------------
252 //----- ANSEL or ANSEL0 ----------------------------------------------------
255 //----- ANSEL1 -------------------------------------------------------------
258 //----- WPUA --------------------------------------------------------------
261 //----- IOC --------------------------------------------------------------
264 //----- IOCA --------------------------------------------------------------
267 //----- REFCON -------------------------------------------------------------
270 //----- VRCON Bits ---------------------------------------------------------
273 //----- EECON1 -------------------------------------------------------------
276 //----- ADCON1 -------------------------------------------------------------
279 //----- PWMCON1 -------------------------------------------------------------
282 //----- PWMCON0 -------------------------------------------------------------
285 //----- PWMCLK -------------------------------------------------------------
288 //----- PWMPH1 & PWMPH2 ----------------------------------------------------
291 //----- CM1CON0 -------------------------------------------------------------
294 //----- CM2CON0 -------------------------------------------------------------
297 //----- CM2CON1 -------------------------------------------------------------
300 //----- OPA1CON & OPA2CON ---------------------------------------------------
303 //==========================================================================
307 //==========================================================================
310 // __BADRAM H'08'-H'09', H'0D', H'16'-H'17', H'19'-H'1D'
311 // __BADRAM H'88'-H'89', H'8D', H'94', H'97', H'C0'-H'EF'
312 // __BADRAM H'108'-H'109', H'10C'-H'10F', H'115'-H'118', H'11E'-H'16F'
313 // __BADRAM H'188'-H'189', H'18C'-H'1EF'
315 //==========================================================================
317 // Configuration Bits
319 //==========================================================================
321 #define _FCMEN_ON 0x3FFF
322 #define _FCMEN_OFF 0x37FF
323 #define _IESO_ON 0x3FFF
324 #define _IESO_OFF 0x3BFF
325 #define _BOD_ON 0x3FFF
326 #define _BOD_NSLEEP 0x3EFF
327 #define _BOD_SBODEN 0x3DFF
328 #define _BOD_OFF 0x3CFF
329 #define _BOR_ON 0x3FFF
330 #define _BOR_NSLEEP 0x3EFF
331 #define _BOR_SBOREN 0x3DFF
332 #define _BOR_OFF 0x3CFF
333 #define _CPD_ON 0x3F7F
334 #define _CPD_OFF 0x3FFF
335 #define _CP_ON 0x3FBF
336 #define _CP_OFF 0x3FFF
337 #define _MCLRE_ON 0x3FFF
338 #define _MCLRE_OFF 0x3FDF
339 #define _PWRTE_OFF 0x3FFF
340 #define _PWRTE_ON 0x3FEF
341 #define _WDT_ON 0x3FFF
342 #define _WDT_OFF 0x3FF7
343 #define _LP_OSC 0x3FF8
344 #define _XT_OSC 0x3FF9
345 #define _HS_OSC 0x3FFA
346 #define _EC_OSC 0x3FFB
347 #define _INTRC_OSC_NOCLKOUT 0x3FFC
348 #define _INTRC_OSC_CLKOUT 0x3FFD
349 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
350 #define _EXTRC_OSC_CLKOUT 0x3FFF
351 #define _INTOSCIO 0x3FFC
352 #define _INTOSC 0x3FFD
353 #define _EXTRCIO 0x3FFE
354 #define _EXTRC 0x3FFF
358 // ----- ADCON0 bits --------------------
361 unsigned char ADON:1;
363 unsigned char CHS0:1;
364 unsigned char CHS1:1;
365 unsigned char CHS2:1;
366 unsigned char CHS3:1;
367 unsigned char VCFG:1;
368 unsigned char ADFM:1;
372 unsigned char NOT_DONE:1;
382 unsigned char GO_DONE:1;
391 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
393 #define ADON ADCON0_bits.ADON
394 #define GO ADCON0_bits.GO
395 #define NOT_DONE ADCON0_bits.NOT_DONE
396 #define GO_DONE ADCON0_bits.GO_DONE
397 #define CHS0 ADCON0_bits.CHS0
398 #define CHS1 ADCON0_bits.CHS1
399 #define CHS2 ADCON0_bits.CHS2
400 #define CHS3 ADCON0_bits.CHS3
401 #define VCFG ADCON0_bits.VCFG
402 #define ADFM ADCON0_bits.ADFM
404 // ----- ADCON1 bits --------------------
411 unsigned char ADCS0:1;
412 unsigned char ADCS1:1;
413 unsigned char ADCS2:1;
417 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
419 #define ADCS0 ADCON1_bits.ADCS0
420 #define ADCS1 ADCON1_bits.ADCS1
421 #define ADCS2 ADCON1_bits.ADCS2
423 // ----- ANSEL1 bits --------------------
426 unsigned char ANS8:1;
427 unsigned char ANS9:1;
428 unsigned char ANS10:1;
429 unsigned char ANS11:1;
436 extern volatile __ANSEL1_bits_t __at(ANSEL1_ADDR) ANSEL1_bits;
438 #define ANS8 ANSEL1_bits.ANS8
439 #define ANS9 ANSEL1_bits.ANS9
440 #define ANS10 ANSEL1_bits.ANS10
441 #define ANS11 ANSEL1_bits.ANS11
443 // ----- CCP1CON bits --------------------
446 unsigned char CCP1M0:1;
447 unsigned char CCP1M1:1;
448 unsigned char CCP1M2:1;
449 unsigned char CCP1M3:1;
450 unsigned char DC1B0:1;
451 unsigned char DC1B1:1;
456 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
458 #define CCP1M0 CCP1CON_bits.CCP1M0
459 #define CCP1M1 CCP1CON_bits.CCP1M1
460 #define CCP1M2 CCP1CON_bits.CCP1M2
461 #define CCP1M3 CCP1CON_bits.CCP1M3
462 #define DC1B0 CCP1CON_bits.DC1B0
463 #define DC1B1 CCP1CON_bits.DC1B1
465 // ----- CM1CON0 bits --------------------
468 unsigned char C1CH0:1;
469 unsigned char C1CH1:1;
471 unsigned char C1SP:1;
472 unsigned char C1POL:1;
473 unsigned char C1OE:1;
474 unsigned char C1OUT:1;
475 unsigned char C1ON:1;
478 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
480 #define C1CH0 CM1CON0_bits.C1CH0
481 #define C1CH1 CM1CON0_bits.C1CH1
482 #define C1R CM1CON0_bits.C1R
483 #define C1SP CM1CON0_bits.C1SP
484 #define C1POL CM1CON0_bits.C1POL
485 #define C1OE CM1CON0_bits.C1OE
486 #define C1OUT CM1CON0_bits.C1OUT
487 #define C1ON CM1CON0_bits.C1ON
489 // ----- CM2CON0 bits --------------------
492 unsigned char C2CH0:1;
493 unsigned char C2CH1:1;
495 unsigned char C2SP:1;
496 unsigned char C2POL:1;
497 unsigned char C2OE:1;
498 unsigned char C2OUT:1;
499 unsigned char C2ON:1;
502 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
504 #define C2CH0 CM2CON0_bits.C2CH0
505 #define C2CH1 CM2CON0_bits.C2CH1
506 #define C2R CM2CON0_bits.C2R
507 #define C2SP CM2CON0_bits.C2SP
508 #define C2POL CM2CON0_bits.C2POL
509 #define C2OE CM2CON0_bits.C2OE
510 #define C2OUT CM2CON0_bits.C2OUT
511 #define C2ON CM2CON0_bits.C2ON
513 // ----- CM2CON1 bits --------------------
516 unsigned char C2SYNC:1;
517 unsigned char T1GSS:1;
522 unsigned char MC2OUT:1;
523 unsigned char MC1OUT:1;
533 unsigned char OPAON:1;
536 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
538 #define C2SYNC CM2CON1_bits.C2SYNC
539 #define T1GSS CM2CON1_bits.T1GSS
540 #define MC2OUT CM2CON1_bits.MC2OUT
541 #define MC1OUT CM2CON1_bits.MC1OUT
542 #define OPAON CM2CON1_bits.OPAON
544 // ----- EECON1 bits --------------------
549 unsigned char WREN:1;
550 unsigned char WRERR:1;
557 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
559 #define RD EECON1_bits.RD
560 #define WR EECON1_bits.WR
561 #define WREN EECON1_bits.WREN
562 #define WRERR EECON1_bits.WRERR
564 // ----- INTCON bits --------------------
567 unsigned char RAIF:1;
568 unsigned char INTF:1;
569 unsigned char T0IF:1;
570 unsigned char RAIE:1;
571 unsigned char INTE:1;
572 unsigned char T0IE:1;
573 unsigned char PEIE:1;
577 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
579 #define RAIF INTCON_bits.RAIF
580 #define INTF INTCON_bits.INTF
581 #define T0IF INTCON_bits.T0IF
582 #define RAIE INTCON_bits.RAIE
583 #define INTE INTCON_bits.INTE
584 #define T0IE INTCON_bits.T0IE
585 #define PEIE INTCON_bits.PEIE
586 #define GIE INTCON_bits.GIE
588 // ----- IOC bits --------------------
591 unsigned char IOC0:1;
592 unsigned char IOC1:1;
593 unsigned char IOC2:1;
594 unsigned char IOC3:1;
595 unsigned char IOC4:1;
596 unsigned char IOC5:1;
601 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
603 #define IOC0 IOC_bits.IOC0
604 #define IOC1 IOC_bits.IOC1
605 #define IOC2 IOC_bits.IOC2
606 #define IOC3 IOC_bits.IOC3
607 #define IOC4 IOC_bits.IOC4
608 #define IOC5 IOC_bits.IOC5
610 // ----- IOCA bits --------------------
613 unsigned char IOCA0:1;
614 unsigned char IOCA1:1;
615 unsigned char IOCA2:1;
616 unsigned char IOCA3:1;
617 unsigned char IOCA4:1;
618 unsigned char IOCA5:1;
623 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
625 #define IOCA0 IOCA_bits.IOCA0
626 #define IOCA1 IOCA_bits.IOCA1
627 #define IOCA2 IOCA_bits.IOCA2
628 #define IOCA3 IOCA_bits.IOCA3
629 #define IOCA4 IOCA_bits.IOCA4
630 #define IOCA5 IOCA_bits.IOCA5
632 // ----- OPTION_REG bits --------------------
639 unsigned char T0SE:1;
640 unsigned char T0CS:1;
641 unsigned char INTEDG:1;
642 unsigned char NOT_RAPU:1;
644 } __OPTION_REG_bits_t;
645 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
647 #define PS0 OPTION_REG_bits.PS0
648 #define PS1 OPTION_REG_bits.PS1
649 #define PS2 OPTION_REG_bits.PS2
650 #define PSA OPTION_REG_bits.PSA
651 #define T0SE OPTION_REG_bits.T0SE
652 #define T0CS OPTION_REG_bits.T0CS
653 #define INTEDG OPTION_REG_bits.INTEDG
654 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
656 // ----- OSCCON bits --------------------
662 unsigned char OSTS:1;
663 unsigned char IRCF0:1;
664 unsigned char IRCF1:1;
665 unsigned char IRCF2:1;
669 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
671 #define SCS OSCCON_bits.SCS
672 #define LTS OSCCON_bits.LTS
673 #define HTS OSCCON_bits.HTS
674 #define OSTS OSCCON_bits.OSTS
675 #define IRCF0 OSCCON_bits.IRCF0
676 #define IRCF1 OSCCON_bits.IRCF1
677 #define IRCF2 OSCCON_bits.IRCF2
679 // ----- OSCTUNE bits --------------------
682 unsigned char TUN0:1;
683 unsigned char TUN1:1;
684 unsigned char TUN2:1;
685 unsigned char TUN3:1;
686 unsigned char TUN4:1;
687 unsigned char ANS5:1;
688 unsigned char ANS6:1;
689 unsigned char ANS7:1;
692 unsigned char ANS0:1;
693 unsigned char ANS1:1;
694 unsigned char ANS2:1;
695 unsigned char ANS3:1;
696 unsigned char ANS4:1;
702 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
704 #define TUN0 OSCTUNE_bits.TUN0
705 #define ANS0 OSCTUNE_bits.ANS0
706 #define TUN1 OSCTUNE_bits.TUN1
707 #define ANS1 OSCTUNE_bits.ANS1
708 #define TUN2 OSCTUNE_bits.TUN2
709 #define ANS2 OSCTUNE_bits.ANS2
710 #define TUN3 OSCTUNE_bits.TUN3
711 #define ANS3 OSCTUNE_bits.ANS3
712 #define TUN4 OSCTUNE_bits.TUN4
713 #define ANS4 OSCTUNE_bits.ANS4
714 #define ANS5 OSCTUNE_bits.ANS5
715 #define ANS6 OSCTUNE_bits.ANS6
716 #define ANS7 OSCTUNE_bits.ANS7
718 // ----- PCON bits --------------------
721 unsigned char NOT_BOD:1;
722 unsigned char NOT_POR:1;
725 unsigned char SBODEN:1;
731 unsigned char NOT_BOR:1;
735 unsigned char SBOREN:1;
741 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
743 #define NOT_BOD PCON_bits.NOT_BOD
744 #define NOT_BOR PCON_bits.NOT_BOR
745 #define NOT_POR PCON_bits.NOT_POR
746 #define SBODEN PCON_bits.SBODEN
747 #define SBOREN PCON_bits.SBOREN
749 // ----- PIE1 bits --------------------
752 unsigned char T1IE:1;
753 unsigned char T2IE:1;
754 unsigned char OSFIE:1;
755 unsigned char C1IE:1;
756 unsigned char C2IE:1;
757 unsigned char CCP1IE:1;
758 unsigned char ADIE:1;
759 unsigned char EEIE:1;
762 unsigned char TMR1IE:1;
763 unsigned char TMR2IE:1;
772 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
774 #define T1IE PIE1_bits.T1IE
775 #define TMR1IE PIE1_bits.TMR1IE
776 #define T2IE PIE1_bits.T2IE
777 #define TMR2IE PIE1_bits.TMR2IE
778 #define OSFIE PIE1_bits.OSFIE
779 #define C1IE PIE1_bits.C1IE
780 #define C2IE PIE1_bits.C2IE
781 #define CCP1IE PIE1_bits.CCP1IE
782 #define ADIE PIE1_bits.ADIE
783 #define EEIE PIE1_bits.EEIE
785 // ----- PIR1 bits --------------------
788 unsigned char T1IF:1;
789 unsigned char T2IF:1;
790 unsigned char OSFIF:1;
791 unsigned char C1IF:1;
792 unsigned char C2IF:1;
793 unsigned char CCP1IF:1;
794 unsigned char ADIF:1;
795 unsigned char EEIF:1;
798 unsigned char TMR1IF:1;
799 unsigned char TMR2IF:1;
808 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
810 #define T1IF PIR1_bits.T1IF
811 #define TMR1IF PIR1_bits.TMR1IF
812 #define T2IF PIR1_bits.T2IF
813 #define TMR2IF PIR1_bits.TMR2IF
814 #define OSFIF PIR1_bits.OSFIF
815 #define C1IF PIR1_bits.C1IF
816 #define C2IF PIR1_bits.C2IF
817 #define CCP1IF PIR1_bits.CCP1IF
818 #define ADIF PIR1_bits.ADIF
819 #define EEIF PIR1_bits.EEIF
821 // ----- PORTA bits --------------------
834 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
836 #define RA0 PORTA_bits.RA0
837 #define RA1 PORTA_bits.RA1
838 #define RA2 PORTA_bits.RA2
839 #define RA3 PORTA_bits.RA3
840 #define RA4 PORTA_bits.RA4
841 #define RA5 PORTA_bits.RA5
843 // ----- PORTB bits --------------------
856 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
858 #define RB0 PORTB_bits.RB0
859 #define RB1 PORTB_bits.RB1
860 #define RB2 PORTB_bits.RB2
861 #define RB3 PORTB_bits.RB3
862 #define RB4 PORTB_bits.RB4
863 #define RB5 PORTB_bits.RB5
864 #define RB6 PORTB_bits.RB6
865 #define RB7 PORTB_bits.RB7
867 // ----- PORTC bits --------------------
880 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
882 #define RC0 PORTC_bits.RC0
883 #define RC1 PORTC_bits.RC1
884 #define RC2 PORTC_bits.RC2
885 #define RC3 PORTC_bits.RC3
886 #define RC4 PORTC_bits.RC4
887 #define RC5 PORTC_bits.RC5
888 #define RC6 PORTC_bits.RC6
889 #define RC7 PORTC_bits.RC7
891 // ----- PWMCLK bits --------------------
894 unsigned char PER0:1;
895 unsigned char PER1:1;
896 unsigned char PER2:1;
897 unsigned char PER3:1;
898 unsigned char PER4:1;
899 unsigned char PWMP0:1;
900 unsigned char PWMP1:1;
901 unsigned char PWMASE:1;
909 unsigned char C1EN:1;
910 unsigned char C2EN:1;
914 extern volatile __PWMCLK_bits_t __at(PWMCLK_ADDR) PWMCLK_bits;
916 #define PER0 PWMCLK_bits.PER0
917 #define PH0 PWMCLK_bits.PH0
918 #define PER1 PWMCLK_bits.PER1
919 #define PH1 PWMCLK_bits.PH1
920 #define PER2 PWMCLK_bits.PER2
921 #define PH2 PWMCLK_bits.PH2
922 #define PER3 PWMCLK_bits.PER3
923 #define PH3 PWMCLK_bits.PH3
924 #define PER4 PWMCLK_bits.PER4
925 #define PH4 PWMCLK_bits.PH4
926 #define PWMP0 PWMCLK_bits.PWMP0
927 #define C1EN PWMCLK_bits.C1EN
928 #define PWMP1 PWMCLK_bits.PWMP1
929 #define C2EN PWMCLK_bits.C2EN
930 #define PWMASE PWMCLK_bits.PWMASE
931 #define POL PWMCLK_bits.POL
933 // ----- PWMCON0 bits --------------------
936 unsigned char PH1EN:1;
937 unsigned char PH2EN:1;
938 unsigned char SYNC0:1;
939 unsigned char SYNC1:1;
940 unsigned char BLANK1:1;
941 unsigned char BLANK2:1;
942 unsigned char PASEN:1;
943 unsigned char PRSEN:1;
946 extern volatile __PWMCON0_bits_t __at(PWMCON0_ADDR) PWMCON0_bits;
948 #define PH1EN PWMCON0_bits.PH1EN
949 #define PH2EN PWMCON0_bits.PH2EN
950 #define SYNC0 PWMCON0_bits.SYNC0
951 #define SYNC1 PWMCON0_bits.SYNC1
952 #define BLANK1 PWMCON0_bits.BLANK1
953 #define BLANK2 PWMCON0_bits.BLANK2
954 #define PASEN PWMCON0_bits.PASEN
955 #define PRSEN PWMCON0_bits.PRSEN
957 // ----- PWMCON1 bits --------------------
960 unsigned char CMDLY0:1;
961 unsigned char CMDLY1:1;
962 unsigned char CMDLY2:1;
963 unsigned char CMDLY3:1;
964 unsigned char CMDLY4:1;
965 unsigned char COMOD0:1;
966 unsigned char COMOD1:1;
970 extern volatile __PWMCON1_bits_t __at(PWMCON1_ADDR) PWMCON1_bits;
972 #define CMDLY0 PWMCON1_bits.CMDLY0
973 #define CMDLY1 PWMCON1_bits.CMDLY1
974 #define CMDLY2 PWMCON1_bits.CMDLY2
975 #define CMDLY3 PWMCON1_bits.CMDLY3
976 #define CMDLY4 PWMCON1_bits.CMDLY4
977 #define COMOD0 PWMCON1_bits.COMOD0
978 #define COMOD1 PWMCON1_bits.COMOD1
980 // ----- REFCON bits --------------------
984 unsigned char CVROE:1;
985 unsigned char VROE:1;
986 unsigned char VREN:1;
987 unsigned char VRBB:1;
988 unsigned char BGST:1;
993 extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits;
995 #define CVROE REFCON_bits.CVROE
996 #define VROE REFCON_bits.VROE
997 #define VREN REFCON_bits.VREN
998 #define VRBB REFCON_bits.VRBB
999 #define BGST REFCON_bits.BGST
1001 // ----- STATUS bits --------------------
1007 unsigned char NOT_PD:1;
1008 unsigned char NOT_TO:1;
1009 unsigned char RP0:1;
1010 unsigned char RP1:1;
1011 unsigned char IRP:1;
1014 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1016 #define C STATUS_bits.C
1017 #define DC STATUS_bits.DC
1018 #define Z STATUS_bits.Z
1019 #define NOT_PD STATUS_bits.NOT_PD
1020 #define NOT_TO STATUS_bits.NOT_TO
1021 #define RP0 STATUS_bits.RP0
1022 #define RP1 STATUS_bits.RP1
1023 #define IRP STATUS_bits.IRP
1025 // ----- T1CON bits --------------------
1028 unsigned char TMR1ON:1;
1029 unsigned char TMR1CS:1;
1030 unsigned char NOT_T1SYNC:1;
1031 unsigned char T1OSCEN:1;
1032 unsigned char T1CKPS0:1;
1033 unsigned char T1CKPS1:1;
1034 unsigned char TMR1GE:1;
1035 unsigned char T1GINV:1;
1044 unsigned char T1GE:1;
1048 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1050 #define TMR1ON T1CON_bits.TMR1ON
1051 #define TMR1CS T1CON_bits.TMR1CS
1052 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1053 #define T1OSCEN T1CON_bits.T1OSCEN
1054 #define T1CKPS0 T1CON_bits.T1CKPS0
1055 #define T1CKPS1 T1CON_bits.T1CKPS1
1056 #define TMR1GE T1CON_bits.TMR1GE
1057 #define T1GE T1CON_bits.T1GE
1058 #define T1GINV T1CON_bits.T1GINV
1060 // ----- T2CON bits --------------------
1063 unsigned char T2CKPS0:1;
1064 unsigned char T2CKPS1:1;
1065 unsigned char TMR2ON:1;
1066 unsigned char TOUTPS0:1;
1067 unsigned char TOUTPS1:1;
1068 unsigned char TOUTPS2:1;
1069 unsigned char TOUTPS3:1;
1073 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1075 #define T2CKPS0 T2CON_bits.T2CKPS0
1076 #define T2CKPS1 T2CON_bits.T2CKPS1
1077 #define TMR2ON T2CON_bits.TMR2ON
1078 #define TOUTPS0 T2CON_bits.TOUTPS0
1079 #define TOUTPS1 T2CON_bits.TOUTPS1
1080 #define TOUTPS2 T2CON_bits.TOUTPS2
1081 #define TOUTPS3 T2CON_bits.TOUTPS3
1083 // ----- TRISA bits --------------------
1086 unsigned char TRISA0:1;
1087 unsigned char TRISA1:1;
1088 unsigned char TRISA2:1;
1089 unsigned char TRISA3:1;
1090 unsigned char TRISA4:1;
1091 unsigned char TRISA5:1;
1096 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1098 #define TRISA0 TRISA_bits.TRISA0
1099 #define TRISA1 TRISA_bits.TRISA1
1100 #define TRISA2 TRISA_bits.TRISA2
1101 #define TRISA3 TRISA_bits.TRISA3
1102 #define TRISA4 TRISA_bits.TRISA4
1103 #define TRISA5 TRISA_bits.TRISA5
1105 // ----- TRISB bits --------------------
1108 unsigned char TRISB0:1;
1109 unsigned char TRISB1:1;
1110 unsigned char TRISB2:1;
1111 unsigned char TRISB3:1;
1112 unsigned char TRISB4:1;
1113 unsigned char TRISB5:1;
1114 unsigned char TRISB6:1;
1115 unsigned char TRISB7:1;
1118 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1120 #define TRISB0 TRISB_bits.TRISB0
1121 #define TRISB1 TRISB_bits.TRISB1
1122 #define TRISB2 TRISB_bits.TRISB2
1123 #define TRISB3 TRISB_bits.TRISB3
1124 #define TRISB4 TRISB_bits.TRISB4
1125 #define TRISB5 TRISB_bits.TRISB5
1126 #define TRISB6 TRISB_bits.TRISB6
1127 #define TRISB7 TRISB_bits.TRISB7
1129 // ----- TRISC bits --------------------
1132 unsigned char TRISC0:1;
1133 unsigned char TRISC1:1;
1134 unsigned char TRISC2:1;
1135 unsigned char TRISC3:1;
1136 unsigned char TRISC4:1;
1137 unsigned char TRISC5:1;
1138 unsigned char TRISC6:1;
1139 unsigned char TRISC7:1;
1142 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1144 #define TRISC0 TRISC_bits.TRISC0
1145 #define TRISC1 TRISC_bits.TRISC1
1146 #define TRISC2 TRISC_bits.TRISC2
1147 #define TRISC3 TRISC_bits.TRISC3
1148 #define TRISC4 TRISC_bits.TRISC4
1149 #define TRISC5 TRISC_bits.TRISC5
1150 #define TRISC6 TRISC_bits.TRISC6
1151 #define TRISC7 TRISC_bits.TRISC7
1153 // ----- VRCON bits --------------------
1156 unsigned char VR0:1;
1157 unsigned char VR1:1;
1158 unsigned char VR2:1;
1159 unsigned char VR3:1;
1161 unsigned char VRR:1;
1162 unsigned char C2VREN:1;
1163 unsigned char C1VREN:1;
1166 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1168 #define VR0 VRCON_bits.VR0
1169 #define VR1 VRCON_bits.VR1
1170 #define VR2 VRCON_bits.VR2
1171 #define VR3 VRCON_bits.VR3
1172 #define VRR VRCON_bits.VRR
1173 #define C2VREN VRCON_bits.C2VREN
1174 #define C1VREN VRCON_bits.C1VREN
1176 // ----- WDTCON bits --------------------
1179 unsigned char SWDTEN:1;
1180 unsigned char WDTPS0:1;
1181 unsigned char WDTPS1:1;
1182 unsigned char WDTPS2:1;
1183 unsigned char WDTPS3:1;
1189 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1191 #define SWDTEN WDTCON_bits.SWDTEN
1192 #define WDTPS0 WDTCON_bits.WDTPS0
1193 #define WDTPS1 WDTCON_bits.WDTPS1
1194 #define WDTPS2 WDTCON_bits.WDTPS2
1195 #define WDTPS3 WDTCON_bits.WDTPS3
1197 // ----- WPUA bits --------------------
1200 unsigned char WPUA0:1;
1201 unsigned char WPUA1:1;
1202 unsigned char WPUA2:1;
1203 unsigned char WPUA3:1;
1204 unsigned char WPUA4:1;
1205 unsigned char WPUA5:1;
1210 extern volatile __WPUA_bits_t __at(WPUA_ADDR) WPUA_bits;
1212 #define WPUA0 WPUA_bits.WPUA0
1213 #define WPUA1 WPUA_bits.WPUA1
1214 #define WPUA2 WPUA_bits.WPUA2
1215 #define WPUA3 WPUA_bits.WPUA3
1216 #define WPUA4 WPUA_bits.WPUA4
1217 #define WPUA5 WPUA_bits.WPUA5