2 // Register Declarations for Microchip 16F690 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define PWM1CON_ADDR 0x001C
54 #define ECCPAS_ADDR 0x001D
55 #define ADRESH_ADDR 0x001E
56 #define ADCON0_ADDR 0x001F
57 #define OPTION_REG_ADDR 0x0081
58 #define TRISA_ADDR 0x0085
59 #define TRISB_ADDR 0x0086
60 #define TRISC_ADDR 0x0087
61 #define PIE1_ADDR 0x008C
62 #define PIE2_ADDR 0x008D
63 #define PCON_ADDR 0x008E
64 #define OSCCON_ADDR 0x008F
65 #define OSCTUNE_ADDR 0x0090
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define MSK_ADDR 0x0093
69 #define SSPMSK_ADDR 0x0093
70 #define SSPSTAT_ADDR 0x0094
71 #define WPU_ADDR 0x0095
72 #define WPUA_ADDR 0x0095
73 #define IOC_ADDR 0x0096
74 #define IOCA_ADDR 0x0096
75 #define WDTCON_ADDR 0x0097
76 #define TXSTA_ADDR 0x0098
77 #define SPBRG_ADDR 0x0099
78 #define SPBRGH_ADDR 0x009A
79 #define BAUDCTL_ADDR 0x009B
80 #define ADRESL_ADDR 0x009E
81 #define ADCON1_ADDR 0x009F
82 #define EEDAT_ADDR 0x010C
83 #define EEDATA_ADDR 0x010C
84 #define EEADR_ADDR 0x010D
85 #define EEDATH_ADDR 0x010E
86 #define EEADRH_ADDR 0x010F
87 #define WPUB_ADDR 0x0115
88 #define IOCB_ADDR 0x0116
89 #define VRCON_ADDR 0x0118
90 #define CM1CON0_ADDR 0x0119
91 #define CM2CON0_ADDR 0x011A
92 #define CM2CON1_ADDR 0x011B
93 #define ANSEL_ADDR 0x011E
94 #define ANSELH_ADDR 0x011F
95 #define EECON1_ADDR 0x018C
96 #define EECON2_ADDR 0x018D
97 #define PSTRCON_ADDR 0x019D
98 #define SRCON_ADDR 0x019E
101 // Memory organization.
107 // P16F690.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
110 // This header file defines configurations, registers, and other useful bits of
111 // information for the PIC16F690 microcontroller. These names are taken to match
112 // the data sheets as closely as possible.
114 // Note that the processor must be selected before this file is
115 // included. The processor may be selected the following ways:
117 // 1. Command line switch:
118 // C:\ MPASM MYFILE.ASM /PIC16F690
119 // 2. LIST directive in the source file
121 // 3. Processor Type entry in the MPASM full-screen interface
123 //==========================================================================
127 //==========================================================================
128 //1.00 10/12/04 Original
129 //==========================================================================
133 //==========================================================================
136 // MESSG "Processor-header file mismatch. Verify selected processor."
139 //==========================================================================
141 // Register Definitions
143 //==========================================================================
148 //----- Register Files------------------------------------------------------
150 extern __sfr __at (INDF_ADDR) INDF;
151 extern __sfr __at (TMR0_ADDR) TMR0;
152 extern __sfr __at (PCL_ADDR) PCL;
153 extern __sfr __at (STATUS_ADDR) STATUS;
154 extern __sfr __at (FSR_ADDR) FSR;
155 extern __sfr __at (PORTA_ADDR) PORTA;
156 extern __sfr __at (PORTB_ADDR) PORTB;
157 extern __sfr __at (PORTC_ADDR) PORTC;
159 extern __sfr __at (PCLATH_ADDR) PCLATH;
160 extern __sfr __at (INTCON_ADDR) INTCON;
161 extern __sfr __at (PIR1_ADDR) PIR1;
162 extern __sfr __at (PIR2_ADDR) PIR2;
163 extern __sfr __at (TMR1L_ADDR) TMR1L;
164 extern __sfr __at (TMR1H_ADDR) TMR1H;
165 extern __sfr __at (T1CON_ADDR) T1CON;
166 extern __sfr __at (TMR2_ADDR) TMR2;
167 extern __sfr __at (T2CON_ADDR) T2CON;
168 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
169 extern __sfr __at (SSPCON_ADDR) SSPCON;
170 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
171 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
172 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
173 extern __sfr __at (RCSTA_ADDR) RCSTA;
174 extern __sfr __at (TXREG_ADDR) TXREG;
175 extern __sfr __at (RCREG_ADDR) RCREG;
177 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
178 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
179 extern __sfr __at (ADRESH_ADDR) ADRESH;
180 extern __sfr __at (ADCON0_ADDR) ADCON0;
183 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
185 extern __sfr __at (TRISA_ADDR) TRISA;
186 extern __sfr __at (TRISB_ADDR) TRISB;
187 extern __sfr __at (TRISC_ADDR) TRISC;
189 extern __sfr __at (PIE1_ADDR) PIE1;
190 extern __sfr __at (PIE2_ADDR) PIE2;
191 extern __sfr __at (PCON_ADDR) PCON;
192 extern __sfr __at (OSCCON_ADDR) OSCCON;
193 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
195 extern __sfr __at (PR2_ADDR) PR2;
196 extern __sfr __at (SSPADD_ADDR) SSPADD;
197 extern __sfr __at (MSK_ADDR) MSK;
198 extern __sfr __at (SSPMSK_ADDR) SSPMSK;
199 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
200 extern __sfr __at (WPU_ADDR) WPU;
201 extern __sfr __at (WPUA_ADDR) WPUA;
202 extern __sfr __at (IOC_ADDR) IOC;
203 extern __sfr __at (IOCA_ADDR) IOCA;
204 extern __sfr __at (WDTCON_ADDR) WDTCON;
205 extern __sfr __at (TXSTA_ADDR) TXSTA;
206 extern __sfr __at (SPBRG_ADDR) SPBRG;
207 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
208 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
211 extern __sfr __at (ADRESL_ADDR) ADRESL;
212 extern __sfr __at (ADCON1_ADDR) ADCON1;
215 extern __sfr __at (EEDAT_ADDR) EEDAT;
216 extern __sfr __at (EEDATA_ADDR) EEDATA;
217 extern __sfr __at (EEADR_ADDR) EEADR;
218 extern __sfr __at (EEDATH_ADDR) EEDATH;
219 extern __sfr __at (EEADRH_ADDR) EEADRH;
222 extern __sfr __at (WPUB_ADDR) WPUB;
223 extern __sfr __at (IOCB_ADDR) IOCB;
225 extern __sfr __at (VRCON_ADDR) VRCON;
226 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
227 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
228 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
230 extern __sfr __at (ANSEL_ADDR) ANSEL;
231 extern __sfr __at (ANSELH_ADDR) ANSELH;
233 extern __sfr __at (EECON1_ADDR) EECON1;
234 extern __sfr __at (EECON2_ADDR) EECON2;
237 extern __sfr __at (PSTRCON_ADDR) PSTRCON;
238 extern __sfr __at (SRCON_ADDR) SRCON;
242 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
243 //----- STATUS Bits --------------------------------------------------------
246 //----- INTCON Bits --------------------------------------------------------
249 //----- PIR1 Bits ----------------------------------------------------------
252 //----- PIR2 Bits ----------------------------------------------------------
255 //----- T1CON Bits ---------------------------------------------------------
258 //----- T2CON Bits ---------------------------------------------------------
261 //----- SSPCON Bits -------------------------------------------------------
264 //----- CCP1CON Bits -------------------------------------------------------
267 //----- RCSTA Bits ---------------------------------------------------------
270 //----- PWM1CON Bits -------------------------------------------------------
273 //----- ECCPAS Bits --------------------------------------------------------
276 //----- ADCON0 Bits --------------------------------------------------------
279 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
280 //----- OPTION Bits --------------------------------------------------------
283 //----- TRISA Bits --------------------------------------------------------
286 //----- TRISB Bits --------------------------------------------------------
289 //----- TRISC Bits --------------------------------------------------------
292 //----- PIE1 Bits ----------------------------------------------------------
295 //----- PIE2 Bits ----------------------------------------------------------
298 //----- PCON Bits ----------------------------------------------------------
301 //----- OSCCON Bits --------------------------------------------------------
304 //----- OSCTUNE Bits -------------------------------------------------------
307 //----- SSPSTAT Bits --------------------------------------------------------
310 //----- WPUA --------------------------------------------------------------
314 //----- IOC --------------------------------------------------------------
317 //----- IOCA --------------------------------------------------------------
320 //----- WDTCON Bits --------------------------------------------------------
323 //----- TXSTA Bits -------------------------------------------------------
326 //----- SPBRG Bits -------------------------------------------------------
329 //----- SPBRGH Bits -------------------------------------------------------
332 //----- BAUDCTL Bits -------------------------------------------------------
337 //----- ADCON1 -------------------------------------------------------------
340 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
341 //----- WPUB Bits ----------------------------------------------------------
344 //----- IOCB --------------------------------------------------------------
347 //----- VRCON Bits ---------------------------------------------------------
350 //----- CM1CON0 Bits -------------------------------------------------------
354 //----- CM2CON0 Bits -------------------------------------------------------
358 //----- CM2CON1 Bits -------------------------------------------------------
361 //----- ANSELH -------------------------------------------------------------
364 //----- ANSEL --------------------------------------------------------------
367 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
368 //----- EECON1 -------------------------------------------------------------
371 //----- PSTRCON -------------------------------------------------------------
374 //----- SRCON ---------------------------------------------------------------
377 //==========================================================================
381 //==========================================================================
384 // __BADRAM H'08'-H'09', H'1B'
385 // __BADRAM H'88'-H'89', H'91', H'9C'-H'9D'
386 // __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D'
387 // __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF'
389 //==========================================================================
391 // Configuration Bits
393 //==========================================================================
395 #define _FCMEN_ON 0x3FFF
396 #define _FCMEN_OFF 0x37FF
397 #define _IESO_ON 0x3FFF
398 #define _IESO_OFF 0x3BFF
399 #define _BOR_ON 0x3FFF
400 #define _BOR_NSLEEP 0x3EFF
401 #define _BOR_SBODEN 0x3DFF
402 #define _BOR_OFF 0x3CFF
403 #define _CPD_ON 0x3F7F
404 #define _CPD_OFF 0x3FFF
405 #define _CP_ON 0x3FBF
406 #define _CP_OFF 0x3FFF
407 #define _MCLRE_ON 0x3FFF
408 #define _MCLRE_OFF 0x3FDF
409 #define _PWRTE_OFF 0x3FFF
410 #define _PWRTE_ON 0x3FEF
411 #define _WDT_ON 0x3FFF
412 #define _WDT_OFF 0x3FF7
413 #define _LP_OSC 0x3FF8
414 #define _XT_OSC 0x3FF9
415 #define _HS_OSC 0x3FFA
416 #define _EC_OSC 0x3FFB
417 #define _INTRC_OSC_NOCLKOUT 0x3FFC
418 #define _INTRC_OSC_CLKOUT 0x3FFD
419 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
420 #define _EXTRC_OSC_CLKOUT 0x3FFF
421 #define _INTOSCIO 0x3FFC
422 #define _INTOSC 0x3FFD
423 #define _EXTRCIO 0x3FFE
424 #define _EXTRC 0x3FFF
428 // ----- ADCON0 bits --------------------
431 unsigned char ADON:1;
433 unsigned char CHS0:1;
434 unsigned char CHS1:1;
435 unsigned char CHS2:1;
436 unsigned char CHS3:1;
437 unsigned char VCFG:1;
438 unsigned char ADFM:1;
442 unsigned char NOT_DONE:1;
452 unsigned char GO_DONE:1;
461 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
463 #define ADON ADCON0_bits.ADON
464 #define GO ADCON0_bits.GO
465 #define NOT_DONE ADCON0_bits.NOT_DONE
466 #define GO_DONE ADCON0_bits.GO_DONE
467 #define CHS0 ADCON0_bits.CHS0
468 #define CHS1 ADCON0_bits.CHS1
469 #define CHS2 ADCON0_bits.CHS2
470 #define CHS3 ADCON0_bits.CHS3
471 #define VCFG ADCON0_bits.VCFG
472 #define ADFM ADCON0_bits.ADFM
474 // ----- ADCON1 bits --------------------
481 unsigned char ADCS0:1;
482 unsigned char ADCS1:1;
483 unsigned char ADCS2:1;
487 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
489 #define ADCS0 ADCON1_bits.ADCS0
490 #define ADCS1 ADCON1_bits.ADCS1
491 #define ADCS2 ADCON1_bits.ADCS2
493 // ----- ANSEL bits --------------------
496 unsigned char ANS0:1;
497 unsigned char ANS1:1;
498 unsigned char ANS2:1;
499 unsigned char ANS3:1;
500 unsigned char ANS4:1;
501 unsigned char ANS5:1;
502 unsigned char ANS6:1;
503 unsigned char ANS7:1;
506 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
508 #define ANS0 ANSEL_bits.ANS0
509 #define ANS1 ANSEL_bits.ANS1
510 #define ANS2 ANSEL_bits.ANS2
511 #define ANS3 ANSEL_bits.ANS3
512 #define ANS4 ANSEL_bits.ANS4
513 #define ANS5 ANSEL_bits.ANS5
514 #define ANS6 ANSEL_bits.ANS6
515 #define ANS7 ANSEL_bits.ANS7
517 // ----- ANSELH bits --------------------
520 unsigned char ANS8:1;
521 unsigned char ANS9:1;
522 unsigned char ANS10:1;
523 unsigned char ANS11:1;
530 extern volatile __ANSELH_bits_t __at(ANSELH_ADDR) ANSELH_bits;
532 #define ANS8 ANSELH_bits.ANS8
533 #define ANS9 ANSELH_bits.ANS9
534 #define ANS10 ANSELH_bits.ANS10
535 #define ANS11 ANSELH_bits.ANS11
537 // ----- BAUDCTL bits --------------------
540 unsigned char ABDEN:1;
543 unsigned char BRG16:1;
544 unsigned char SCKP:1;
546 unsigned char RCIDL:1;
547 unsigned char ABDOVF:1;
550 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
552 #define ABDEN BAUDCTL_bits.ABDEN
553 #define WUE BAUDCTL_bits.WUE
554 #define BRG16 BAUDCTL_bits.BRG16
555 #define SCKP BAUDCTL_bits.SCKP
556 #define RCIDL BAUDCTL_bits.RCIDL
557 #define ABDOVF BAUDCTL_bits.ABDOVF
559 // ----- CCP1CON bits --------------------
562 unsigned char CCP1M0:1;
563 unsigned char CCP1M1:1;
564 unsigned char CCP1M2:1;
565 unsigned char CCP1M3:1;
566 unsigned char DC1B0:1;
567 unsigned char DC1B1:1;
568 unsigned char P1M0:1;
569 unsigned char P1M1:1;
572 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
574 #define CCP1M0 CCP1CON_bits.CCP1M0
575 #define CCP1M1 CCP1CON_bits.CCP1M1
576 #define CCP1M2 CCP1CON_bits.CCP1M2
577 #define CCP1M3 CCP1CON_bits.CCP1M3
578 #define DC1B0 CCP1CON_bits.DC1B0
579 #define DC1B1 CCP1CON_bits.DC1B1
580 #define P1M0 CCP1CON_bits.P1M0
581 #define P1M1 CCP1CON_bits.P1M1
583 // ----- CM1CON0 bits --------------------
586 unsigned char C1CH0:1;
587 unsigned char C1CH1:1;
590 unsigned char C1POL:1;
591 unsigned char C1OE:1;
592 unsigned char C1OUT:1;
593 unsigned char C1ON:1;
596 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
598 #define C1CH0 CM1CON0_bits.C1CH0
599 #define C1CH1 CM1CON0_bits.C1CH1
600 #define C1R CM1CON0_bits.C1R
601 #define C1POL CM1CON0_bits.C1POL
602 #define C1OE CM1CON0_bits.C1OE
603 #define C1OUT CM1CON0_bits.C1OUT
604 #define C1ON CM1CON0_bits.C1ON
606 // ----- CM2CON0 bits --------------------
609 unsigned char C2CH0:1;
610 unsigned char C2CH1:1;
613 unsigned char C2POL:1;
614 unsigned char C2OE:1;
615 unsigned char C2OUT:1;
616 unsigned char C2ON:1;
619 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
621 #define C2CH0 CM2CON0_bits.C2CH0
622 #define C2CH1 CM2CON0_bits.C2CH1
623 #define C2R CM2CON0_bits.C2R
624 #define C2POL CM2CON0_bits.C2POL
625 #define C2OE CM2CON0_bits.C2OE
626 #define C2OUT CM2CON0_bits.C2OUT
627 #define C2ON CM2CON0_bits.C2ON
629 // ----- CM2CON1 bits --------------------
632 unsigned char C2SYNC:1;
633 unsigned char T1GSS:1;
638 unsigned char MC2OUT:1;
639 unsigned char MC1OUT:1;
642 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
644 #define C2SYNC CM2CON1_bits.C2SYNC
645 #define T1GSS CM2CON1_bits.T1GSS
646 #define MC2OUT CM2CON1_bits.MC2OUT
647 #define MC1OUT CM2CON1_bits.MC1OUT
649 // ----- ECCPAS bits --------------------
652 unsigned char PSSBD0:1;
653 unsigned char PSSBD1:1;
654 unsigned char PSSAC0:1;
655 unsigned char PSSAC1:1;
656 unsigned char ECCPAS0:1;
657 unsigned char ECCPAS1:1;
658 unsigned char ECCPAS2:1;
659 unsigned char ECCPASE:1;
662 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
664 #define PSSBD0 ECCPAS_bits.PSSBD0
665 #define PSSBD1 ECCPAS_bits.PSSBD1
666 #define PSSAC0 ECCPAS_bits.PSSAC0
667 #define PSSAC1 ECCPAS_bits.PSSAC1
668 #define ECCPAS0 ECCPAS_bits.ECCPAS0
669 #define ECCPAS1 ECCPAS_bits.ECCPAS1
670 #define ECCPAS2 ECCPAS_bits.ECCPAS2
671 #define ECCPASE ECCPAS_bits.ECCPASE
673 // ----- EECON1 bits --------------------
678 unsigned char WREN:1;
679 unsigned char WRERR:1;
683 unsigned char EEPGD:1;
686 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
688 #define RD EECON1_bits.RD
689 #define WR EECON1_bits.WR
690 #define WREN EECON1_bits.WREN
691 #define WRERR EECON1_bits.WRERR
692 #define EEPGD EECON1_bits.EEPGD
694 // ----- INTCON bits --------------------
697 unsigned char RABIF:1;
698 unsigned char INTF:1;
699 unsigned char T0IF:1;
700 unsigned char RABIE:1;
701 unsigned char INTE:1;
702 unsigned char T0IE:1;
703 unsigned char PEIE:1;
707 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
709 #define RABIF INTCON_bits.RABIF
710 #define INTF INTCON_bits.INTF
711 #define T0IF INTCON_bits.T0IF
712 #define RABIE INTCON_bits.RABIE
713 #define INTE INTCON_bits.INTE
714 #define T0IE INTCON_bits.T0IE
715 #define PEIE INTCON_bits.PEIE
716 #define GIE INTCON_bits.GIE
718 // ----- IOC bits --------------------
721 unsigned char IOC0:1;
722 unsigned char IOC1:1;
723 unsigned char IOC2:1;
724 unsigned char IOC3:1;
725 unsigned char IOC4:1;
726 unsigned char IOC5:1;
731 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
733 #define IOC0 IOC_bits.IOC0
734 #define IOC1 IOC_bits.IOC1
735 #define IOC2 IOC_bits.IOC2
736 #define IOC3 IOC_bits.IOC3
737 #define IOC4 IOC_bits.IOC4
738 #define IOC5 IOC_bits.IOC5
740 // ----- IOCA bits --------------------
743 unsigned char IOCA0:1;
744 unsigned char IOCA1:1;
745 unsigned char IOCA2:1;
746 unsigned char IOCA3:1;
747 unsigned char IOCA4:1;
748 unsigned char IOCA5:1;
753 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
755 #define IOCA0 IOCA_bits.IOCA0
756 #define IOCA1 IOCA_bits.IOCA1
757 #define IOCA2 IOCA_bits.IOCA2
758 #define IOCA3 IOCA_bits.IOCA3
759 #define IOCA4 IOCA_bits.IOCA4
760 #define IOCA5 IOCA_bits.IOCA5
762 // ----- IOCB bits --------------------
769 unsigned char IOCB4:1;
770 unsigned char IOCB5:1;
771 unsigned char IOCB6:1;
772 unsigned char IOCB7:1;
775 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
777 #define IOCB4 IOCB_bits.IOCB4
778 #define IOCB5 IOCB_bits.IOCB5
779 #define IOCB6 IOCB_bits.IOCB6
780 #define IOCB7 IOCB_bits.IOCB7
782 // ----- OPTION_REG bits --------------------
789 unsigned char T0SE:1;
790 unsigned char T0CS:1;
791 unsigned char INTEDG:1;
792 unsigned char NOT_RABPU:1;
794 } __OPTION_REG_bits_t;
795 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
797 #define PS0 OPTION_REG_bits.PS0
798 #define PS1 OPTION_REG_bits.PS1
799 #define PS2 OPTION_REG_bits.PS2
800 #define PSA OPTION_REG_bits.PSA
801 #define T0SE OPTION_REG_bits.T0SE
802 #define T0CS OPTION_REG_bits.T0CS
803 #define INTEDG OPTION_REG_bits.INTEDG
804 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
806 // ----- OSCCON bits --------------------
812 unsigned char OSTS:1;
813 unsigned char IRCF0:1;
814 unsigned char IRCF1:1;
815 unsigned char IRCF2:1;
819 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
821 #define SCS OSCCON_bits.SCS
822 #define LTS OSCCON_bits.LTS
823 #define HTS OSCCON_bits.HTS
824 #define OSTS OSCCON_bits.OSTS
825 #define IRCF0 OSCCON_bits.IRCF0
826 #define IRCF1 OSCCON_bits.IRCF1
827 #define IRCF2 OSCCON_bits.IRCF2
829 // ----- OSCTUNE bits --------------------
832 unsigned char TUN0:1;
833 unsigned char TUN1:1;
834 unsigned char TUN2:1;
835 unsigned char TUN3:1;
836 unsigned char TUN4:1;
842 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
844 #define TUN0 OSCTUNE_bits.TUN0
845 #define TUN1 OSCTUNE_bits.TUN1
846 #define TUN2 OSCTUNE_bits.TUN2
847 #define TUN3 OSCTUNE_bits.TUN3
848 #define TUN4 OSCTUNE_bits.TUN4
850 // ----- PCON bits --------------------
853 unsigned char NOT_BOR:1;
854 unsigned char NOT_POR:1;
857 unsigned char SBOREN:1;
858 unsigned char ULPWUE:1;
863 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
865 #define NOT_BOR PCON_bits.NOT_BOR
866 #define NOT_POR PCON_bits.NOT_POR
867 #define SBOREN PCON_bits.SBOREN
868 #define ULPWUE PCON_bits.ULPWUE
870 // ----- PIE1 bits --------------------
873 unsigned char T1IE:1;
874 unsigned char T2IE:1;
875 unsigned char CCP1IE:1;
876 unsigned char SSPIE:1;
877 unsigned char TXIE:1;
878 unsigned char RCIE:1;
879 unsigned char ADIE:1;
883 unsigned char TMR1IE:1;
884 unsigned char TMR2IE:1;
893 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
895 #define T1IE PIE1_bits.T1IE
896 #define TMR1IE PIE1_bits.TMR1IE
897 #define T2IE PIE1_bits.T2IE
898 #define TMR2IE PIE1_bits.TMR2IE
899 #define CCP1IE PIE1_bits.CCP1IE
900 #define SSPIE PIE1_bits.SSPIE
901 #define TXIE PIE1_bits.TXIE
902 #define RCIE PIE1_bits.RCIE
903 #define ADIE PIE1_bits.ADIE
905 // ----- PIE2 bits --------------------
912 unsigned char EEIE:1;
913 unsigned char C1IE:1;
914 unsigned char C2IE:1;
915 unsigned char OSFIE:1;
918 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
920 #define EEIE PIE2_bits.EEIE
921 #define C1IE PIE2_bits.C1IE
922 #define C2IE PIE2_bits.C2IE
923 #define OSFIE PIE2_bits.OSFIE
925 // ----- PIR1 bits --------------------
928 unsigned char T1IF:1;
929 unsigned char T2IF:1;
930 unsigned char CCP1IF:1;
931 unsigned char SSPIF:1;
932 unsigned char TXIF:1;
933 unsigned char RCIF:1;
934 unsigned char ADIF:1;
938 unsigned char TMR1IF:1;
939 unsigned char TMR2IF:1;
948 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
950 #define T1IF PIR1_bits.T1IF
951 #define TMR1IF PIR1_bits.TMR1IF
952 #define T2IF PIR1_bits.T2IF
953 #define TMR2IF PIR1_bits.TMR2IF
954 #define CCP1IF PIR1_bits.CCP1IF
955 #define SSPIF PIR1_bits.SSPIF
956 #define TXIF PIR1_bits.TXIF
957 #define RCIF PIR1_bits.RCIF
958 #define ADIF PIR1_bits.ADIF
960 // ----- PIR2 bits --------------------
967 unsigned char EEIF:1;
968 unsigned char C1IF:1;
969 unsigned char C2IF:1;
970 unsigned char OSFIF:1;
973 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
975 #define EEIF PIR2_bits.EEIF
976 #define C1IF PIR2_bits.C1IF
977 #define C2IF PIR2_bits.C2IF
978 #define OSFIF PIR2_bits.OSFIF
980 // ----- PORTA bits --------------------
993 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
995 #define RA0 PORTA_bits.RA0
996 #define RA1 PORTA_bits.RA1
997 #define RA2 PORTA_bits.RA2
998 #define RA3 PORTA_bits.RA3
999 #define RA4 PORTA_bits.RA4
1000 #define RA5 PORTA_bits.RA5
1002 // ----- PORTB bits --------------------
1005 unsigned char RB0:1;
1006 unsigned char RB1:1;
1007 unsigned char RB2:1;
1008 unsigned char RB3:1;
1009 unsigned char RB4:1;
1010 unsigned char RB5:1;
1011 unsigned char RB6:1;
1012 unsigned char RB7:1;
1015 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
1017 #define RB0 PORTB_bits.RB0
1018 #define RB1 PORTB_bits.RB1
1019 #define RB2 PORTB_bits.RB2
1020 #define RB3 PORTB_bits.RB3
1021 #define RB4 PORTB_bits.RB4
1022 #define RB5 PORTB_bits.RB5
1023 #define RB6 PORTB_bits.RB6
1024 #define RB7 PORTB_bits.RB7
1026 // ----- PORTC bits --------------------
1029 unsigned char RC0:1;
1030 unsigned char RC1:1;
1031 unsigned char RC2:1;
1032 unsigned char RC3:1;
1033 unsigned char RC4:1;
1034 unsigned char RC5:1;
1035 unsigned char RC6:1;
1036 unsigned char RC7:1;
1039 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
1041 #define RC0 PORTC_bits.RC0
1042 #define RC1 PORTC_bits.RC1
1043 #define RC2 PORTC_bits.RC2
1044 #define RC3 PORTC_bits.RC3
1045 #define RC4 PORTC_bits.RC4
1046 #define RC5 PORTC_bits.RC5
1047 #define RC6 PORTC_bits.RC6
1048 #define RC7 PORTC_bits.RC7
1050 // ----- PSTRCON bits --------------------
1053 unsigned char STRA:1;
1054 unsigned char STRB:1;
1055 unsigned char STRC:1;
1056 unsigned char STRD:1;
1057 unsigned char STRSYNC:1;
1063 extern volatile __PSTRCON_bits_t __at(PSTRCON_ADDR) PSTRCON_bits;
1065 #define STRA PSTRCON_bits.STRA
1066 #define STRB PSTRCON_bits.STRB
1067 #define STRC PSTRCON_bits.STRC
1068 #define STRD PSTRCON_bits.STRD
1069 #define STRSYNC PSTRCON_bits.STRSYNC
1071 // ----- PWM1CON bits --------------------
1074 unsigned char PDC0:1;
1075 unsigned char PDC1:1;
1076 unsigned char PDC2:1;
1077 unsigned char PDC3:1;
1078 unsigned char PDC4:1;
1079 unsigned char PDC5:1;
1080 unsigned char PDC6:1;
1081 unsigned char PRSEN:1;
1084 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
1086 #define PDC0 PWM1CON_bits.PDC0
1087 #define PDC1 PWM1CON_bits.PDC1
1088 #define PDC2 PWM1CON_bits.PDC2
1089 #define PDC3 PWM1CON_bits.PDC3
1090 #define PDC4 PWM1CON_bits.PDC4
1091 #define PDC5 PWM1CON_bits.PDC5
1092 #define PDC6 PWM1CON_bits.PDC6
1093 #define PRSEN PWM1CON_bits.PRSEN
1095 // ----- RCSTA bits --------------------
1098 unsigned char RX9D:1;
1099 unsigned char OERR:1;
1100 unsigned char FERR:1;
1101 unsigned char ADDEN:1;
1102 unsigned char CREN:1;
1103 unsigned char SREN:1;
1104 unsigned char RX9:1;
1105 unsigned char SPEN:1;
1108 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
1110 #define RX9D RCSTA_bits.RX9D
1111 #define OERR RCSTA_bits.OERR
1112 #define FERR RCSTA_bits.FERR
1113 #define ADDEN RCSTA_bits.ADDEN
1114 #define CREN RCSTA_bits.CREN
1115 #define SREN RCSTA_bits.SREN
1116 #define RX9 RCSTA_bits.RX9
1117 #define SPEN RCSTA_bits.SPEN
1119 // ----- SPBRG bits --------------------
1122 unsigned char BRG0:1;
1123 unsigned char BRG1:1;
1124 unsigned char BRG2:1;
1125 unsigned char BRG3:1;
1126 unsigned char BRG4:1;
1127 unsigned char BRG5:1;
1128 unsigned char BRG6:1;
1129 unsigned char BRG7:1;
1132 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
1134 #define BRG0 SPBRG_bits.BRG0
1135 #define BRG1 SPBRG_bits.BRG1
1136 #define BRG2 SPBRG_bits.BRG2
1137 #define BRG3 SPBRG_bits.BRG3
1138 #define BRG4 SPBRG_bits.BRG4
1139 #define BRG5 SPBRG_bits.BRG5
1140 #define BRG6 SPBRG_bits.BRG6
1141 #define BRG7 SPBRG_bits.BRG7
1143 // ----- SPBRGH bits --------------------
1146 unsigned char BRG8:1;
1147 unsigned char BRG9:1;
1148 unsigned char BRG10:1;
1149 unsigned char BRG11:1;
1150 unsigned char BRG12:1;
1151 unsigned char BRG13:1;
1152 unsigned char BRG14:1;
1153 unsigned char BRG15:1;
1156 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
1158 #define BRG8 SPBRGH_bits.BRG8
1159 #define BRG9 SPBRGH_bits.BRG9
1160 #define BRG10 SPBRGH_bits.BRG10
1161 #define BRG11 SPBRGH_bits.BRG11
1162 #define BRG12 SPBRGH_bits.BRG12
1163 #define BRG13 SPBRGH_bits.BRG13
1164 #define BRG14 SPBRGH_bits.BRG14
1165 #define BRG15 SPBRGH_bits.BRG15
1167 // ----- SRCON bits --------------------
1172 unsigned char PULSR:1;
1173 unsigned char PULSS:1;
1174 unsigned char C2REN:1;
1175 unsigned char C1SEN:1;
1176 unsigned char SR0:1;
1177 unsigned char SR1:1;
1180 extern volatile __SRCON_bits_t __at(SRCON_ADDR) SRCON_bits;
1182 #define PULSR SRCON_bits.PULSR
1183 #define PULSS SRCON_bits.PULSS
1184 #define C2REN SRCON_bits.C2REN
1185 #define C1SEN SRCON_bits.C1SEN
1186 #define SR0 SRCON_bits.SR0
1187 #define SR1 SRCON_bits.SR1
1189 // ----- SSPCON bits --------------------
1192 unsigned char SSPM0:1;
1193 unsigned char SSPM1:1;
1194 unsigned char SSPM2:1;
1195 unsigned char SSPM3:1;
1196 unsigned char CKP:1;
1197 unsigned char SSPEN:1;
1198 unsigned char SSPOV:1;
1199 unsigned char WCOL:1;
1202 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1204 #define SSPM0 SSPCON_bits.SSPM0
1205 #define SSPM1 SSPCON_bits.SSPM1
1206 #define SSPM2 SSPCON_bits.SSPM2
1207 #define SSPM3 SSPCON_bits.SSPM3
1208 #define CKP SSPCON_bits.CKP
1209 #define SSPEN SSPCON_bits.SSPEN
1210 #define SSPOV SSPCON_bits.SSPOV
1211 #define WCOL SSPCON_bits.WCOL
1213 // ----- SSPSTAT bits --------------------
1222 unsigned char CKE:1;
1223 unsigned char SMP:1;
1228 unsigned char I2C_READ:1;
1229 unsigned char I2C_START:1;
1230 unsigned char I2C_STOP:1;
1231 unsigned char I2C_DATA:1;
1238 unsigned char NOT_W:1;
1241 unsigned char NOT_A:1;
1248 unsigned char NOT_WRITE:1;
1251 unsigned char NOT_ADDRESS:1;
1258 unsigned char R_W:1;
1261 unsigned char D_A:1;
1268 unsigned char READ_WRITE:1;
1271 unsigned char DATA_ADDRESS:1;
1276 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1278 #define BF SSPSTAT_bits.BF
1279 #define UA SSPSTAT_bits.UA
1280 #define R SSPSTAT_bits.R
1281 #define I2C_READ SSPSTAT_bits.I2C_READ
1282 #define NOT_W SSPSTAT_bits.NOT_W
1283 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1284 #define R_W SSPSTAT_bits.R_W
1285 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1286 #define S SSPSTAT_bits.S
1287 #define I2C_START SSPSTAT_bits.I2C_START
1288 #define P SSPSTAT_bits.P
1289 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1290 #define D SSPSTAT_bits.D
1291 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1292 #define NOT_A SSPSTAT_bits.NOT_A
1293 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1294 #define D_A SSPSTAT_bits.D_A
1295 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1296 #define CKE SSPSTAT_bits.CKE
1297 #define SMP SSPSTAT_bits.SMP
1299 // ----- STATUS bits --------------------
1305 unsigned char NOT_PD:1;
1306 unsigned char NOT_TO:1;
1307 unsigned char RP0:1;
1308 unsigned char RP1:1;
1309 unsigned char IRP:1;
1312 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1314 #define C STATUS_bits.C
1315 #define DC STATUS_bits.DC
1316 #define Z STATUS_bits.Z
1317 #define NOT_PD STATUS_bits.NOT_PD
1318 #define NOT_TO STATUS_bits.NOT_TO
1319 #define RP0 STATUS_bits.RP0
1320 #define RP1 STATUS_bits.RP1
1321 #define IRP STATUS_bits.IRP
1323 // ----- T1CON bits --------------------
1326 unsigned char TMR1ON:1;
1327 unsigned char TMR1CS:1;
1328 unsigned char NOT_T1SYNC:1;
1329 unsigned char T1OSCEN:1;
1330 unsigned char T1CKPS0:1;
1331 unsigned char T1CKPS1:1;
1332 unsigned char TMR1GE:1;
1333 unsigned char T1GINV:1;
1336 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1338 #define TMR1ON T1CON_bits.TMR1ON
1339 #define TMR1CS T1CON_bits.TMR1CS
1340 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1341 #define T1OSCEN T1CON_bits.T1OSCEN
1342 #define T1CKPS0 T1CON_bits.T1CKPS0
1343 #define T1CKPS1 T1CON_bits.T1CKPS1
1344 #define TMR1GE T1CON_bits.TMR1GE
1345 #define T1GINV T1CON_bits.T1GINV
1347 // ----- T2CON bits --------------------
1350 unsigned char T2CKPS0:1;
1351 unsigned char T2CKPS1:1;
1352 unsigned char TMR2ON:1;
1353 unsigned char TOUTPS0:1;
1354 unsigned char TOUTPS1:1;
1355 unsigned char TOUTPS2:1;
1356 unsigned char TOUTPS3:1;
1360 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1362 #define T2CKPS0 T2CON_bits.T2CKPS0
1363 #define T2CKPS1 T2CON_bits.T2CKPS1
1364 #define TMR2ON T2CON_bits.TMR2ON
1365 #define TOUTPS0 T2CON_bits.TOUTPS0
1366 #define TOUTPS1 T2CON_bits.TOUTPS1
1367 #define TOUTPS2 T2CON_bits.TOUTPS2
1368 #define TOUTPS3 T2CON_bits.TOUTPS3
1370 // ----- TRISA bits --------------------
1373 unsigned char TRISA0:1;
1374 unsigned char TRISA1:1;
1375 unsigned char TRISA2:1;
1376 unsigned char TRISA3:1;
1377 unsigned char TRISA4:1;
1378 unsigned char TRISA5:1;
1383 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1385 #define TRISA0 TRISA_bits.TRISA0
1386 #define TRISA1 TRISA_bits.TRISA1
1387 #define TRISA2 TRISA_bits.TRISA2
1388 #define TRISA3 TRISA_bits.TRISA3
1389 #define TRISA4 TRISA_bits.TRISA4
1390 #define TRISA5 TRISA_bits.TRISA5
1392 // ----- TRISB bits --------------------
1399 unsigned char TRISB4:1;
1400 unsigned char TRISB5:1;
1401 unsigned char TRISB6:1;
1402 unsigned char TRISB7:1;
1405 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1407 #define TRISB4 TRISB_bits.TRISB4
1408 #define TRISB5 TRISB_bits.TRISB5
1409 #define TRISB6 TRISB_bits.TRISB6
1410 #define TRISB7 TRISB_bits.TRISB7
1412 // ----- TRISC bits --------------------
1415 unsigned char TRISC0:1;
1416 unsigned char TRISC1:1;
1417 unsigned char TRISC2:1;
1418 unsigned char TRISC3:1;
1419 unsigned char TRISC4:1;
1420 unsigned char TRISC5:1;
1421 unsigned char TRISC6:1;
1422 unsigned char TRISC7:1;
1425 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1427 #define TRISC0 TRISC_bits.TRISC0
1428 #define TRISC1 TRISC_bits.TRISC1
1429 #define TRISC2 TRISC_bits.TRISC2
1430 #define TRISC3 TRISC_bits.TRISC3
1431 #define TRISC4 TRISC_bits.TRISC4
1432 #define TRISC5 TRISC_bits.TRISC5
1433 #define TRISC6 TRISC_bits.TRISC6
1434 #define TRISC7 TRISC_bits.TRISC7
1436 // ----- TXSTA bits --------------------
1439 unsigned char TX9D:1;
1440 unsigned char TRMT:1;
1441 unsigned char BRGH:1;
1442 unsigned char SENB:1;
1443 unsigned char SYNC:1;
1444 unsigned char TXEN:1;
1445 unsigned char TX9:1;
1446 unsigned char CSRC:1;
1449 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1451 #define TX9D TXSTA_bits.TX9D
1452 #define TRMT TXSTA_bits.TRMT
1453 #define BRGH TXSTA_bits.BRGH
1454 #define SENB TXSTA_bits.SENB
1455 #define SYNC TXSTA_bits.SYNC
1456 #define TXEN TXSTA_bits.TXEN
1457 #define TX9 TXSTA_bits.TX9
1458 #define CSRC TXSTA_bits.CSRC
1460 // ----- VRCON bits --------------------
1463 unsigned char VR0:1;
1464 unsigned char VR1:1;
1465 unsigned char VR2:1;
1466 unsigned char VR3:1;
1467 unsigned char VP6EN:1;
1468 unsigned char VRR:1;
1469 unsigned char C2VREN:1;
1470 unsigned char C1VREN:1;
1473 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1475 #define VR0 VRCON_bits.VR0
1476 #define VR1 VRCON_bits.VR1
1477 #define VR2 VRCON_bits.VR2
1478 #define VR3 VRCON_bits.VR3
1479 #define VP6EN VRCON_bits.VP6EN
1480 #define VRR VRCON_bits.VRR
1481 #define C2VREN VRCON_bits.C2VREN
1482 #define C1VREN VRCON_bits.C1VREN
1484 // ----- WDTCON bits --------------------
1487 unsigned char SWDTEN:1;
1488 unsigned char WDTPS0:1;
1489 unsigned char WDTPS1:1;
1490 unsigned char WDTPS2:1;
1491 unsigned char WDTPS3:1;
1497 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1499 #define SWDTEN WDTCON_bits.SWDTEN
1500 #define WDTPS0 WDTCON_bits.WDTPS0
1501 #define WDTPS1 WDTCON_bits.WDTPS1
1502 #define WDTPS2 WDTCON_bits.WDTPS2
1503 #define WDTPS3 WDTCON_bits.WDTPS3
1505 // ----- WPUA bits --------------------
1508 unsigned char WPUA0:1;
1509 unsigned char WPUA1:1;
1510 unsigned char WPUA2:1;
1512 unsigned char WPUA4:1;
1513 unsigned char WPUA5:1;
1518 extern volatile __WPUA_bits_t __at(WPUA_ADDR) WPUA_bits;
1520 #define WPUA0 WPUA_bits.WPUA0
1521 #define WPUA1 WPUA_bits.WPUA1
1522 #define WPUA2 WPUA_bits.WPUA2
1523 #define WPUA4 WPUA_bits.WPUA4
1524 #define WPUA5 WPUA_bits.WPUA5
1526 // ----- WPUB bits --------------------
1533 unsigned char WPUB4:1;
1534 unsigned char WPUB5:1;
1535 unsigned char WPUB6:1;
1536 unsigned char WPUB7:1;
1539 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1541 #define WPUB4 WPUB_bits.WPUB4
1542 #define WPUB5 WPUB_bits.WPUB5
1543 #define WPUB6 WPUB_bits.WPUB6
1544 #define WPUB7 WPUB_bits.WPUB7