2 // Register Declarations for Microchip 16F685 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define CCPR1L_ADDR 0x0015
46 #define CCPR1H_ADDR 0x0016
47 #define CCP1CON_ADDR 0x0017
48 #define PWM1CON_ADDR 0x001C
49 #define ECCPAS_ADDR 0x001D
50 #define ADRESH_ADDR 0x001E
51 #define ADCON0_ADDR 0x001F
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PIE2_ADDR 0x008D
58 #define PCON_ADDR 0x008E
59 #define OSCCON_ADDR 0x008F
60 #define OSCTUNE_ADDR 0x0090
61 #define PR2_ADDR 0x0092
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define WDTCON_ADDR 0x0097
67 #define ADRESL_ADDR 0x009E
68 #define ADCON1_ADDR 0x009F
69 #define EEDAT_ADDR 0x010C
70 #define EEDATA_ADDR 0x010C
71 #define EEADR_ADDR 0x010D
72 #define EEDATH_ADDR 0x010E
73 #define EEADRH_ADDR 0x010F
74 #define WPUB_ADDR 0x0115
75 #define IOCB_ADDR 0x0116
76 #define VRCON_ADDR 0x0118
77 #define CM1CON0_ADDR 0x0119
78 #define CM2CON0_ADDR 0x011A
79 #define CM2CON1_ADDR 0x011B
80 #define ANSEL_ADDR 0x011E
81 #define ANSELH_ADDR 0x011F
82 #define EECON1_ADDR 0x018C
83 #define EECON2_ADDR 0x018D
84 #define PSTRCON_ADDR 0x019D
85 #define SRCON_ADDR 0x019E
88 // Memory organization.
94 // P16F685.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
97 // This header file defines configurations, registers, and other useful bits of
98 // information for the PIC16F685 microcontroller. These names are taken to match
99 // the data sheets as closely as possible.
101 // Note that the processor must be selected before this file is
102 // included. The processor may be selected the following ways:
104 // 1. Command line switch:
105 // C:\ MPASM MYFILE.ASM /PIC16F685
106 // 2. LIST directive in the source file
108 // 3. Processor Type entry in the MPASM full-screen interface
110 //==========================================================================
114 //==========================================================================
115 //1.00 10/12/04 Original
116 //2.00 04/21/05 Modified file to match released datasheet
117 //==========================================================================
121 //==========================================================================
124 // MESSG "Processor-header file mismatch. Verify selected processor."
127 //==========================================================================
129 // Register Definitions
131 //==========================================================================
136 //----- Register Files------------------------------------------------------
138 extern __sfr __at (INDF_ADDR) INDF;
139 extern __sfr __at (TMR0_ADDR) TMR0;
140 extern __sfr __at (PCL_ADDR) PCL;
141 extern __sfr __at (STATUS_ADDR) STATUS;
142 extern __sfr __at (FSR_ADDR) FSR;
143 extern __sfr __at (PORTA_ADDR) PORTA;
144 extern __sfr __at (PORTB_ADDR) PORTB;
145 extern __sfr __at (PORTC_ADDR) PORTC;
147 extern __sfr __at (PCLATH_ADDR) PCLATH;
148 extern __sfr __at (INTCON_ADDR) INTCON;
149 extern __sfr __at (PIR1_ADDR) PIR1;
150 extern __sfr __at (PIR2_ADDR) PIR2;
151 extern __sfr __at (TMR1L_ADDR) TMR1L;
152 extern __sfr __at (TMR1H_ADDR) TMR1H;
153 extern __sfr __at (T1CON_ADDR) T1CON;
154 extern __sfr __at (TMR2_ADDR) TMR2;
155 extern __sfr __at (T2CON_ADDR) T2CON;
158 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
159 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
160 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
163 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
164 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
165 extern __sfr __at (ADRESH_ADDR) ADRESH;
166 extern __sfr __at (ADCON0_ADDR) ADCON0;
169 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
171 extern __sfr __at (TRISA_ADDR) TRISA;
172 extern __sfr __at (TRISB_ADDR) TRISB;
173 extern __sfr __at (TRISC_ADDR) TRISC;
175 extern __sfr __at (PIE1_ADDR) PIE1;
176 extern __sfr __at (PIE2_ADDR) PIE2;
177 extern __sfr __at (PCON_ADDR) PCON;
178 extern __sfr __at (OSCCON_ADDR) OSCCON;
179 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
181 extern __sfr __at (PR2_ADDR) PR2;
184 extern __sfr __at (WPU_ADDR) WPU;
185 extern __sfr __at (WPUA_ADDR) WPUA;
186 extern __sfr __at (IOC_ADDR) IOC;
187 extern __sfr __at (IOCA_ADDR) IOCA;
188 extern __sfr __at (WDTCON_ADDR) WDTCON;
192 extern __sfr __at (ADRESL_ADDR) ADRESL;
193 extern __sfr __at (ADCON1_ADDR) ADCON1;
196 extern __sfr __at (EEDAT_ADDR) EEDAT;
197 extern __sfr __at (EEDATA_ADDR) EEDATA;
198 extern __sfr __at (EEADR_ADDR) EEADR;
199 extern __sfr __at (EEDATH_ADDR) EEDATH;
200 extern __sfr __at (EEADRH_ADDR) EEADRH;
203 extern __sfr __at (WPUB_ADDR) WPUB;
204 extern __sfr __at (IOCB_ADDR) IOCB;
206 extern __sfr __at (VRCON_ADDR) VRCON;
207 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
208 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
209 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
211 extern __sfr __at (ANSEL_ADDR) ANSEL;
212 extern __sfr __at (ANSELH_ADDR) ANSELH;
214 extern __sfr __at (EECON1_ADDR) EECON1;
215 extern __sfr __at (EECON2_ADDR) EECON2;
218 extern __sfr __at (PSTRCON_ADDR) PSTRCON;
219 extern __sfr __at (SRCON_ADDR) SRCON;
223 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
224 //----- STATUS Bits --------------------------------------------------------
227 //----- INTCON Bits --------------------------------------------------------
230 //----- PIR1 Bits ----------------------------------------------------------
235 //----- PIR2 Bits ----------------------------------------------------------
238 //----- T1CON Bits ---------------------------------------------------------
241 //----- T2CON Bits ---------------------------------------------------------
245 //----- CCP1CON Bits -------------------------------------------------------
248 //----- PWM1CON Bits -------------------------------------------------------
251 //----- ECCPAS Bits --------------------------------------------------------
254 //----- ADCON0 Bits --------------------------------------------------------
257 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
258 //----- OPTION Bits --------------------------------------------------------
261 //----- TRISA Bits --------------------------------------------------------
264 //----- TRISB Bits --------------------------------------------------------
267 //----- TRISC Bits --------------------------------------------------------
270 //----- PIE1 Bits ----------------------------------------------------------
275 //----- PIE2 Bits ----------------------------------------------------------
278 //----- PCON Bits ----------------------------------------------------------
281 //----- OSCCON Bits --------------------------------------------------------
284 //----- OSCTUNE Bits -------------------------------------------------------
287 //----- WPUA --------------------------------------------------------------
291 //----- IOC --------------------------------------------------------------
294 //----- IOCA --------------------------------------------------------------
297 //----- WDTCON Bits --------------------------------------------------------
300 //----- ADCON1 -------------------------------------------------------------
303 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
304 //----- WPUB Bits ----------------------------------------------------------
307 //----- IOCB --------------------------------------------------------------
310 //----- VRCON Bits ---------------------------------------------------------
313 //----- CM1CON0 Bits -------------------------------------------------------
317 //----- CM2CON0 Bits -------------------------------------------------------
321 //----- CM2CON1 Bits -------------------------------------------------------
324 //----- ANSELH --------------------------------------------------------------
327 //----- ANSEL --------------------------------------------------------------
330 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
331 //----- EECON1 -------------------------------------------------------------
334 //----- PSTRCON -------------------------------------------------------------
337 //----- SRCON ---------------------------------------------------------------
340 //==========================================================================
344 //==========================================================================
347 // __BADRAM H'08'-H'09', H'13'-H'14', H'18'-H'1B'
348 // __BADRAM H'88'-H'89', H'91', H'93'-H'94', H'98'-H'9D'
349 // __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D'
350 // __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF'
352 //==========================================================================
354 // Configuration Bits
356 //==========================================================================
358 #define _FCMEN_ON 0x3FFF
359 #define _FCMEN_OFF 0x37FF
360 #define _IESO_ON 0x3FFF
361 #define _IESO_OFF 0x3BFF
362 #define _BOR_ON 0x3FFF
363 #define _BOR_NSLEEP 0x3EFF
364 #define _BOR_SBODEN 0x3DFF
365 #define _BOR_OFF 0x3CFF
366 #define _CPD_ON 0x3F7F
367 #define _CPD_OFF 0x3FFF
368 #define _CP_ON 0x3FBF
369 #define _CP_OFF 0x3FFF
370 #define _MCLRE_ON 0x3FFF
371 #define _MCLRE_OFF 0x3FDF
372 #define _PWRTE_OFF 0x3FFF
373 #define _PWRTE_ON 0x3FEF
374 #define _WDT_ON 0x3FFF
375 #define _WDT_OFF 0x3FF7
376 #define _LP_OSC 0x3FF8
377 #define _XT_OSC 0x3FF9
378 #define _HS_OSC 0x3FFA
379 #define _EC_OSC 0x3FFB
380 #define _INTRC_OSC_NOCLKOUT 0x3FFC
381 #define _INTRC_OSC_CLKOUT 0x3FFD
382 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
383 #define _EXTRC_OSC_CLKOUT 0x3FFF
384 #define _INTOSCIO 0x3FFC
385 #define _INTOSC 0x3FFD
386 #define _EXTRCIO 0x3FFE
387 #define _EXTRC 0x3FFF
391 // ----- ADCON0 bits --------------------
394 unsigned char ADON:1;
396 unsigned char CHS0:1;
397 unsigned char CHS1:1;
398 unsigned char CHS2:1;
399 unsigned char CHS3:1;
400 unsigned char VCFG:1;
401 unsigned char ADFM:1;
405 unsigned char NOT_DONE:1;
415 unsigned char GO_DONE:1;
424 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
426 #define ADON ADCON0_bits.ADON
427 #define GO ADCON0_bits.GO
428 #define NOT_DONE ADCON0_bits.NOT_DONE
429 #define GO_DONE ADCON0_bits.GO_DONE
430 #define CHS0 ADCON0_bits.CHS0
431 #define CHS1 ADCON0_bits.CHS1
432 #define CHS2 ADCON0_bits.CHS2
433 #define CHS3 ADCON0_bits.CHS3
434 #define VCFG ADCON0_bits.VCFG
435 #define ADFM ADCON0_bits.ADFM
437 // ----- ADCON1 bits --------------------
444 unsigned char ADCS0:1;
445 unsigned char ADCS1:1;
446 unsigned char ADCS2:1;
450 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
452 #define ADCS0 ADCON1_bits.ADCS0
453 #define ADCS1 ADCON1_bits.ADCS1
454 #define ADCS2 ADCON1_bits.ADCS2
456 // ----- ANSEL bits --------------------
459 unsigned char ANS0:1;
460 unsigned char ANS1:1;
461 unsigned char ANS2:1;
462 unsigned char ANS3:1;
463 unsigned char ANS4:1;
464 unsigned char ANS5:1;
465 unsigned char ANS6:1;
466 unsigned char ANS7:1;
469 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
471 #define ANS0 ANSEL_bits.ANS0
472 #define ANS1 ANSEL_bits.ANS1
473 #define ANS2 ANSEL_bits.ANS2
474 #define ANS3 ANSEL_bits.ANS3
475 #define ANS4 ANSEL_bits.ANS4
476 #define ANS5 ANSEL_bits.ANS5
477 #define ANS6 ANSEL_bits.ANS6
478 #define ANS7 ANSEL_bits.ANS7
480 // ----- ANSELH bits --------------------
483 unsigned char ANS8:1;
484 unsigned char ANS9:1;
485 unsigned char ANS10:1;
486 unsigned char ANS11:1;
493 extern volatile __ANSELH_bits_t __at(ANSELH_ADDR) ANSELH_bits;
495 #define ANS8 ANSELH_bits.ANS8
496 #define ANS9 ANSELH_bits.ANS9
497 #define ANS10 ANSELH_bits.ANS10
498 #define ANS11 ANSELH_bits.ANS11
500 // ----- CCP1CON bits --------------------
503 unsigned char CCP1M0:1;
504 unsigned char CCP1M1:1;
505 unsigned char CCP1M2:1;
506 unsigned char CCP1M3:1;
507 unsigned char DC1B0:1;
508 unsigned char DC1B1:1;
509 unsigned char P1M0:1;
510 unsigned char P1M1:1;
513 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
515 #define CCP1M0 CCP1CON_bits.CCP1M0
516 #define CCP1M1 CCP1CON_bits.CCP1M1
517 #define CCP1M2 CCP1CON_bits.CCP1M2
518 #define CCP1M3 CCP1CON_bits.CCP1M3
519 #define DC1B0 CCP1CON_bits.DC1B0
520 #define DC1B1 CCP1CON_bits.DC1B1
521 #define P1M0 CCP1CON_bits.P1M0
522 #define P1M1 CCP1CON_bits.P1M1
524 // ----- CM1CON0 bits --------------------
527 unsigned char C1CH0:1;
528 unsigned char C1CH1:1;
531 unsigned char C1POL:1;
532 unsigned char C1OE:1;
533 unsigned char C1OUT:1;
534 unsigned char C1ON:1;
537 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
539 #define C1CH0 CM1CON0_bits.C1CH0
540 #define C1CH1 CM1CON0_bits.C1CH1
541 #define C1R CM1CON0_bits.C1R
542 #define C1POL CM1CON0_bits.C1POL
543 #define C1OE CM1CON0_bits.C1OE
544 #define C1OUT CM1CON0_bits.C1OUT
545 #define C1ON CM1CON0_bits.C1ON
547 // ----- CM2CON0 bits --------------------
550 unsigned char C2CH0:1;
551 unsigned char C2CH1:1;
554 unsigned char C2POL:1;
555 unsigned char C2OE:1;
556 unsigned char C2OUT:1;
557 unsigned char C2ON:1;
560 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
562 #define C2CH0 CM2CON0_bits.C2CH0
563 #define C2CH1 CM2CON0_bits.C2CH1
564 #define C2R CM2CON0_bits.C2R
565 #define C2POL CM2CON0_bits.C2POL
566 #define C2OE CM2CON0_bits.C2OE
567 #define C2OUT CM2CON0_bits.C2OUT
568 #define C2ON CM2CON0_bits.C2ON
570 // ----- CM2CON1 bits --------------------
573 unsigned char C2SYNC:1;
574 unsigned char T1GSS:1;
579 unsigned char MC2OUT:1;
580 unsigned char MC1OUT:1;
583 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
585 #define C2SYNC CM2CON1_bits.C2SYNC
586 #define T1GSS CM2CON1_bits.T1GSS
587 #define MC2OUT CM2CON1_bits.MC2OUT
588 #define MC1OUT CM2CON1_bits.MC1OUT
590 // ----- ECCPAS bits --------------------
593 unsigned char PSSBD0:1;
594 unsigned char PSSBD1:1;
595 unsigned char PSSAC0:1;
596 unsigned char PSSAC1:1;
597 unsigned char ECCPAS0:1;
598 unsigned char ECCPAS1:1;
599 unsigned char ECCPAS2:1;
600 unsigned char ECCPASE:1;
603 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
605 #define PSSBD0 ECCPAS_bits.PSSBD0
606 #define PSSBD1 ECCPAS_bits.PSSBD1
607 #define PSSAC0 ECCPAS_bits.PSSAC0
608 #define PSSAC1 ECCPAS_bits.PSSAC1
609 #define ECCPAS0 ECCPAS_bits.ECCPAS0
610 #define ECCPAS1 ECCPAS_bits.ECCPAS1
611 #define ECCPAS2 ECCPAS_bits.ECCPAS2
612 #define ECCPASE ECCPAS_bits.ECCPASE
614 // ----- EECON1 bits --------------------
619 unsigned char WREN:1;
620 unsigned char WRERR:1;
624 unsigned char EEPGD:1;
627 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
629 #define RD EECON1_bits.RD
630 #define WR EECON1_bits.WR
631 #define WREN EECON1_bits.WREN
632 #define WRERR EECON1_bits.WRERR
633 #define EEPGD EECON1_bits.EEPGD
635 // ----- INTCON bits --------------------
638 unsigned char RABIF:1;
639 unsigned char INTF:1;
640 unsigned char T0IF:1;
641 unsigned char RABIE:1;
642 unsigned char INTE:1;
643 unsigned char T0IE:1;
644 unsigned char PEIE:1;
648 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
650 #define RABIF INTCON_bits.RABIF
651 #define INTF INTCON_bits.INTF
652 #define T0IF INTCON_bits.T0IF
653 #define RABIE INTCON_bits.RABIE
654 #define INTE INTCON_bits.INTE
655 #define T0IE INTCON_bits.T0IE
656 #define PEIE INTCON_bits.PEIE
657 #define GIE INTCON_bits.GIE
659 // ----- IOC bits --------------------
662 unsigned char IOC0:1;
663 unsigned char IOC1:1;
664 unsigned char IOC2:1;
665 unsigned char IOC3:1;
666 unsigned char IOC4:1;
667 unsigned char IOC5:1;
672 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
674 #define IOC0 IOC_bits.IOC0
675 #define IOC1 IOC_bits.IOC1
676 #define IOC2 IOC_bits.IOC2
677 #define IOC3 IOC_bits.IOC3
678 #define IOC4 IOC_bits.IOC4
679 #define IOC5 IOC_bits.IOC5
681 // ----- IOCA bits --------------------
684 unsigned char IOCA0:1;
685 unsigned char IOCA1:1;
686 unsigned char IOCA2:1;
687 unsigned char IOCA3:1;
688 unsigned char IOCA4:1;
689 unsigned char IOCA5:1;
694 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
696 #define IOCA0 IOCA_bits.IOCA0
697 #define IOCA1 IOCA_bits.IOCA1
698 #define IOCA2 IOCA_bits.IOCA2
699 #define IOCA3 IOCA_bits.IOCA3
700 #define IOCA4 IOCA_bits.IOCA4
701 #define IOCA5 IOCA_bits.IOCA5
703 // ----- IOCB bits --------------------
710 unsigned char IOCB4:1;
711 unsigned char IOCB5:1;
712 unsigned char IOCB6:1;
713 unsigned char IOCB7:1;
716 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
718 #define IOCB4 IOCB_bits.IOCB4
719 #define IOCB5 IOCB_bits.IOCB5
720 #define IOCB6 IOCB_bits.IOCB6
721 #define IOCB7 IOCB_bits.IOCB7
723 // ----- OPTION_REG bits --------------------
730 unsigned char T0SE:1;
731 unsigned char T0CS:1;
732 unsigned char INTEDG:1;
733 unsigned char NOT_RABPU:1;
735 } __OPTION_REG_bits_t;
736 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
738 #define PS0 OPTION_REG_bits.PS0
739 #define PS1 OPTION_REG_bits.PS1
740 #define PS2 OPTION_REG_bits.PS2
741 #define PSA OPTION_REG_bits.PSA
742 #define T0SE OPTION_REG_bits.T0SE
743 #define T0CS OPTION_REG_bits.T0CS
744 #define INTEDG OPTION_REG_bits.INTEDG
745 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
747 // ----- OSCCON bits --------------------
753 unsigned char OSTS:1;
754 unsigned char IRCF0:1;
755 unsigned char IRCF1:1;
756 unsigned char IRCF2:1;
760 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
762 #define SCS OSCCON_bits.SCS
763 #define LTS OSCCON_bits.LTS
764 #define HTS OSCCON_bits.HTS
765 #define OSTS OSCCON_bits.OSTS
766 #define IRCF0 OSCCON_bits.IRCF0
767 #define IRCF1 OSCCON_bits.IRCF1
768 #define IRCF2 OSCCON_bits.IRCF2
770 // ----- OSCTUNE bits --------------------
773 unsigned char TUN0:1;
774 unsigned char TUN1:1;
775 unsigned char TUN2:1;
776 unsigned char TUN3:1;
777 unsigned char TUN4:1;
783 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
785 #define TUN0 OSCTUNE_bits.TUN0
786 #define TUN1 OSCTUNE_bits.TUN1
787 #define TUN2 OSCTUNE_bits.TUN2
788 #define TUN3 OSCTUNE_bits.TUN3
789 #define TUN4 OSCTUNE_bits.TUN4
791 // ----- PCON bits --------------------
794 unsigned char NOT_BOD:1;
795 unsigned char NOT_POR:1;
798 unsigned char SBOREN:1;
799 unsigned char ULPWUE:1;
804 unsigned char NOT_BOR:1;
814 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
816 #define NOT_BOD PCON_bits.NOT_BOD
817 #define NOT_BOR PCON_bits.NOT_BOR
818 #define NOT_POR PCON_bits.NOT_POR
819 #define SBOREN PCON_bits.SBOREN
820 #define ULPWUE PCON_bits.ULPWUE
822 // ----- PIE1 bits --------------------
825 unsigned char T1IE:1;
826 unsigned char T2IE:1;
827 unsigned char CCP1IE:1;
831 unsigned char ADIE:1;
835 unsigned char TMR1IE:1;
836 unsigned char TMR2IE:1;
845 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
847 #define T1IE PIE1_bits.T1IE
848 #define TMR1IE PIE1_bits.TMR1IE
849 #define T2IE PIE1_bits.T2IE
850 #define TMR2IE PIE1_bits.TMR2IE
851 #define CCP1IE PIE1_bits.CCP1IE
852 #define ADIE PIE1_bits.ADIE
854 // ----- PIE2 bits --------------------
861 unsigned char EEIE:1;
862 unsigned char C1IE:1;
863 unsigned char C2IE:1;
864 unsigned char OSFIE:1;
867 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
869 #define EEIE PIE2_bits.EEIE
870 #define C1IE PIE2_bits.C1IE
871 #define C2IE PIE2_bits.C2IE
872 #define OSFIE PIE2_bits.OSFIE
874 // ----- PIR1 bits --------------------
877 unsigned char T1IF:1;
878 unsigned char T2IF:1;
879 unsigned char CCP1IF:1;
883 unsigned char ADIF:1;
887 unsigned char TMR1IF:1;
888 unsigned char TMR2IF:1;
897 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
899 #define T1IF PIR1_bits.T1IF
900 #define TMR1IF PIR1_bits.TMR1IF
901 #define T2IF PIR1_bits.T2IF
902 #define TMR2IF PIR1_bits.TMR2IF
903 #define CCP1IF PIR1_bits.CCP1IF
904 #define ADIF PIR1_bits.ADIF
906 // ----- PIR2 bits --------------------
913 unsigned char EEIF:1;
914 unsigned char C1IF:1;
915 unsigned char C2IF:1;
916 unsigned char OSFIF:1;
919 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
921 #define EEIF PIR2_bits.EEIF
922 #define C1IF PIR2_bits.C1IF
923 #define C2IF PIR2_bits.C2IF
924 #define OSFIF PIR2_bits.OSFIF
926 // ----- PORTA bits --------------------
939 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
941 #define RA0 PORTA_bits.RA0
942 #define RA1 PORTA_bits.RA1
943 #define RA2 PORTA_bits.RA2
944 #define RA3 PORTA_bits.RA3
945 #define RA4 PORTA_bits.RA4
946 #define RA5 PORTA_bits.RA5
948 // ----- PORTB bits --------------------
961 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
963 #define RB0 PORTB_bits.RB0
964 #define RB1 PORTB_bits.RB1
965 #define RB2 PORTB_bits.RB2
966 #define RB3 PORTB_bits.RB3
967 #define RB4 PORTB_bits.RB4
968 #define RB5 PORTB_bits.RB5
969 #define RB6 PORTB_bits.RB6
970 #define RB7 PORTB_bits.RB7
972 // ----- PORTC bits --------------------
985 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
987 #define RC0 PORTC_bits.RC0
988 #define RC1 PORTC_bits.RC1
989 #define RC2 PORTC_bits.RC2
990 #define RC3 PORTC_bits.RC3
991 #define RC4 PORTC_bits.RC4
992 #define RC5 PORTC_bits.RC5
993 #define RC6 PORTC_bits.RC6
994 #define RC7 PORTC_bits.RC7
996 // ----- PSTRCON bits --------------------
999 unsigned char STRA:1;
1000 unsigned char STRB:1;
1001 unsigned char STRC:1;
1002 unsigned char STRD:1;
1003 unsigned char STRSYNC:1;
1009 extern volatile __PSTRCON_bits_t __at(PSTRCON_ADDR) PSTRCON_bits;
1011 #define STRA PSTRCON_bits.STRA
1012 #define STRB PSTRCON_bits.STRB
1013 #define STRC PSTRCON_bits.STRC
1014 #define STRD PSTRCON_bits.STRD
1015 #define STRSYNC PSTRCON_bits.STRSYNC
1017 // ----- PWM1CON bits --------------------
1020 unsigned char PDC0:1;
1021 unsigned char PDC1:1;
1022 unsigned char PDC2:1;
1023 unsigned char PDC3:1;
1024 unsigned char PDC4:1;
1025 unsigned char PDC5:1;
1026 unsigned char PDC6:1;
1027 unsigned char PRSEN:1;
1030 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
1032 #define PDC0 PWM1CON_bits.PDC0
1033 #define PDC1 PWM1CON_bits.PDC1
1034 #define PDC2 PWM1CON_bits.PDC2
1035 #define PDC3 PWM1CON_bits.PDC3
1036 #define PDC4 PWM1CON_bits.PDC4
1037 #define PDC5 PWM1CON_bits.PDC5
1038 #define PDC6 PWM1CON_bits.PDC6
1039 #define PRSEN PWM1CON_bits.PRSEN
1041 // ----- SRCON bits --------------------
1046 unsigned char PULSR:1;
1047 unsigned char PULSS:1;
1048 unsigned char C2REN:1;
1049 unsigned char C1SEN:1;
1050 unsigned char SR0:1;
1051 unsigned char SR1:1;
1054 extern volatile __SRCON_bits_t __at(SRCON_ADDR) SRCON_bits;
1056 #define PULSR SRCON_bits.PULSR
1057 #define PULSS SRCON_bits.PULSS
1058 #define C2REN SRCON_bits.C2REN
1059 #define C1SEN SRCON_bits.C1SEN
1060 #define SR0 SRCON_bits.SR0
1061 #define SR1 SRCON_bits.SR1
1063 // ----- STATUS bits --------------------
1069 unsigned char NOT_PD:1;
1070 unsigned char NOT_TO:1;
1071 unsigned char RP0:1;
1072 unsigned char RP1:1;
1073 unsigned char IRP:1;
1076 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1078 #define C STATUS_bits.C
1079 #define DC STATUS_bits.DC
1080 #define Z STATUS_bits.Z
1081 #define NOT_PD STATUS_bits.NOT_PD
1082 #define NOT_TO STATUS_bits.NOT_TO
1083 #define RP0 STATUS_bits.RP0
1084 #define RP1 STATUS_bits.RP1
1085 #define IRP STATUS_bits.IRP
1087 // ----- T1CON bits --------------------
1090 unsigned char TMR1ON:1;
1091 unsigned char TMR1CS:1;
1092 unsigned char NOT_T1SYNC:1;
1093 unsigned char T1OSCEN:1;
1094 unsigned char T1CKPS0:1;
1095 unsigned char T1CKPS1:1;
1096 unsigned char TMR1GE:1;
1097 unsigned char T1GINV:1;
1100 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1102 #define TMR1ON T1CON_bits.TMR1ON
1103 #define TMR1CS T1CON_bits.TMR1CS
1104 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1105 #define T1OSCEN T1CON_bits.T1OSCEN
1106 #define T1CKPS0 T1CON_bits.T1CKPS0
1107 #define T1CKPS1 T1CON_bits.T1CKPS1
1108 #define TMR1GE T1CON_bits.TMR1GE
1109 #define T1GINV T1CON_bits.T1GINV
1111 // ----- T2CON bits --------------------
1114 unsigned char T2CKPS0:1;
1115 unsigned char T2CKPS1:1;
1116 unsigned char TMR2ON:1;
1117 unsigned char TOUTPS0:1;
1118 unsigned char TOUTPS1:1;
1119 unsigned char TOUTPS2:1;
1120 unsigned char TOUTPS3:1;
1124 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1126 #define T2CKPS0 T2CON_bits.T2CKPS0
1127 #define T2CKPS1 T2CON_bits.T2CKPS1
1128 #define TMR2ON T2CON_bits.TMR2ON
1129 #define TOUTPS0 T2CON_bits.TOUTPS0
1130 #define TOUTPS1 T2CON_bits.TOUTPS1
1131 #define TOUTPS2 T2CON_bits.TOUTPS2
1132 #define TOUTPS3 T2CON_bits.TOUTPS3
1134 // ----- TRISA bits --------------------
1137 unsigned char TRISA0:1;
1138 unsigned char TRISA1:1;
1139 unsigned char TRISA2:1;
1140 unsigned char TRISA3:1;
1141 unsigned char TRISA4:1;
1142 unsigned char TRISA5:1;
1147 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1149 #define TRISA0 TRISA_bits.TRISA0
1150 #define TRISA1 TRISA_bits.TRISA1
1151 #define TRISA2 TRISA_bits.TRISA2
1152 #define TRISA3 TRISA_bits.TRISA3
1153 #define TRISA4 TRISA_bits.TRISA4
1154 #define TRISA5 TRISA_bits.TRISA5
1156 // ----- TRISB bits --------------------
1163 unsigned char TRISB4:1;
1164 unsigned char TRISB5:1;
1165 unsigned char TRISB6:1;
1166 unsigned char TRISB7:1;
1169 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1171 #define TRISB4 TRISB_bits.TRISB4
1172 #define TRISB5 TRISB_bits.TRISB5
1173 #define TRISB6 TRISB_bits.TRISB6
1174 #define TRISB7 TRISB_bits.TRISB7
1176 // ----- TRISC bits --------------------
1179 unsigned char TRISC0:1;
1180 unsigned char TRISC1:1;
1181 unsigned char TRISC2:1;
1182 unsigned char TRISC3:1;
1183 unsigned char TRISC4:1;
1184 unsigned char TRISC5:1;
1185 unsigned char TRISC6:1;
1186 unsigned char TRISC7:1;
1189 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1191 #define TRISC0 TRISC_bits.TRISC0
1192 #define TRISC1 TRISC_bits.TRISC1
1193 #define TRISC2 TRISC_bits.TRISC2
1194 #define TRISC3 TRISC_bits.TRISC3
1195 #define TRISC4 TRISC_bits.TRISC4
1196 #define TRISC5 TRISC_bits.TRISC5
1197 #define TRISC6 TRISC_bits.TRISC6
1198 #define TRISC7 TRISC_bits.TRISC7
1200 // ----- VRCON bits --------------------
1203 unsigned char VR0:1;
1204 unsigned char VR1:1;
1205 unsigned char VR2:1;
1206 unsigned char VR3:1;
1207 unsigned char VP6EN:1;
1208 unsigned char VRR:1;
1209 unsigned char C2VREN:1;
1210 unsigned char C1VREN:1;
1213 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1215 #define VR0 VRCON_bits.VR0
1216 #define VR1 VRCON_bits.VR1
1217 #define VR2 VRCON_bits.VR2
1218 #define VR3 VRCON_bits.VR3
1219 #define VP6EN VRCON_bits.VP6EN
1220 #define VRR VRCON_bits.VRR
1221 #define C2VREN VRCON_bits.C2VREN
1222 #define C1VREN VRCON_bits.C1VREN
1224 // ----- WDTCON bits --------------------
1227 unsigned char SWDTEN:1;
1228 unsigned char WDTPS0:1;
1229 unsigned char WDTPS1:1;
1230 unsigned char WDTPS2:1;
1231 unsigned char WDTPS3:1;
1237 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1239 #define SWDTEN WDTCON_bits.SWDTEN
1240 #define WDTPS0 WDTCON_bits.WDTPS0
1241 #define WDTPS1 WDTCON_bits.WDTPS1
1242 #define WDTPS2 WDTCON_bits.WDTPS2
1243 #define WDTPS3 WDTCON_bits.WDTPS3
1245 // ----- WPUA bits --------------------
1248 unsigned char WPUA0:1;
1249 unsigned char WPUA1:1;
1250 unsigned char WPUA2:1;
1252 unsigned char WPUA4:1;
1253 unsigned char WPUA5:1;
1258 extern volatile __WPUA_bits_t __at(WPUA_ADDR) WPUA_bits;
1260 #define WPUA0 WPUA_bits.WPUA0
1261 #define WPUA1 WPUA_bits.WPUA1
1262 #define WPUA2 WPUA_bits.WPUA2
1263 #define WPUA4 WPUA_bits.WPUA4
1264 #define WPUA5 WPUA_bits.WPUA5
1266 // ----- WPUB bits --------------------
1273 unsigned char WPUB4:1;
1274 unsigned char WPUB5:1;
1275 unsigned char WPUB6:1;
1276 unsigned char WPUB7:1;
1279 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1281 #define WPUB4 WPUB_bits.WPUB4
1282 #define WPUB5 WPUB_bits.WPUB5
1283 #define WPUB6 WPUB_bits.WPUB6
1284 #define WPUB7 WPUB_bits.WPUB7